Conexant's semiconductor solution for connected photo frame segment

NEWPORT BEACH, USA: Conexant Systems Inc., a leading supplier of innovative semiconductor solutions for imaging, audio, video and Internet connectivity applications, announced the first in a planned series of new system-on-chip (SoC) solutions targeted at the growing market for “connected” digital photo frames and interactive display appliances (IDAs).

These products integrate Internet connectivity and touch-screen technology. The high-performance CX92735 supports advanced features including streaming media content, MP3 audio playback with slideshow functionality, and Wi-Fi, Bluetooth, and Ethernet connectivity.

“Conexant is a leading provider of solutions for multifunction printers and facsimile applications, and we have applied our proficiency in imaging technologies to deliver a new system-on-chip that allows us to expand into the growing, adjacent connected photo frame segment,” said Christian Scherp, president of Conexant.

“We have extensive expertise in analog and mixed-signal design, firmware and software development, and in-depth applications knowledge. We will continue to leverage these strengths to capitalize on growth opportunities in the areas we address, and provide our customers with innovative solutions that contribute to their success.”

Connected frames and IDAs are offered in a wide variety of form-factors including speakerphones, VoIP phones, and digital photo frames. They can be used in a broad range of video, audio, telephony, and digital signage applications.

For example, connected frames can be used within the home to send or receive text messages, make hands-free VoIP phone calls, and access and view information such as news, recipes, weather, and traffic reports from the Internet.

Additional applications include interactive kiosks, point-of-sale terminals, baby monitors, and home automation, security, and monitoring systems. In addition, wireless operators are beginning to allow subscribers to use connected frames to receive data over the cellular network.

Virage Logic sees strong adoption of 40nm IP product portfolio

FREMONT, USA: Virage Logic Corp. announced that since being named TSMC’s 40nm early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio.

Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company’s silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.

Today, more than 10 customers rely on Virage Logic’s 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.

“Virage Logic has a long, proven track record of being first-to-market at the advanced process technologies and with our extensive 40nm product portfolio, we are proud to offer our customers a competitive advantage at this advanced process node,” said Brani Buric, Virage Logic’s executive vice president, marketing and sales.

“Our SiWare Memory and SiWare Logic products provide designers with a comprehensive dashboard of options for the flexibility needed to efficiently manage design tradeoffs and meet customers’ specific requirements. For example, this dashboard enables our customers to achieve up to a 90% power savings in 40nm G and LP process nodes.

“Our STAR Memory System embedded test and repair offering extends the value we can deliver by enabling customers to dramatically ramp to volume at advanced nodes such as 40nm,” he said. “Finally, our product portfolio is supported by a range of engagement models to best meet the requirements of our fabless, integrated device manufacturer (IDM) and foundry customers.”

“TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic’s procedures and TSMC’s procedures including silicon validation of these advanced technology IP solutions,” said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC.

“These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic’s broad IP portfolio on TSMC’s 40nm process.”

The SPIRIT Consortium approves IP-XACT v1.5

NAPA, USA: The SPIRIT Consortium™, a global non-profit organization focused on establishing multi-faceted IP/tool integration standards that drive sustainable growth in electronic design, has approved version 1.5 of its IP-XACT™ specification for handoff to the IEEE P1685 working group.

The IP-XACT specification provides a machine readable XML structure for IP modules and systems databooks. The XML data documents many different aspects of electronic design elements, enabling designers using IP-XACT tools to automatically create many different expressions of a design in a consistent and correlated way.

Design and verification engineers will benefit from using this specification through the automation testbench creation and exploration.

IP-XACT 1.5 will be handed off to the IEEE Standards Association for consideration as an industry standard. This technical specification, known as the IP-XACT design-exchange format, comprehensively addresses support for integrated multi-vendor ESL and RTL design and verification flows.

The P1685 working group is focused on building industry adoption and ratifying an open industry meta-data standard for IP providers, EDA vendors, and independent design manufacturers to help build real marketplace benefit for efficient design tool and IP integration.

"The SPIRIT Consortium gratefully acknowledges the efforts of its Technical Working Groups for their extensive and dedicated work in bringing the specification to readiness for handoff to the IEEE-SA," said Ralph von Vignau, president of The SPIRIT Consortium. "As The SPIRIT Consortium specifications are adopted, integrated device manufacturers will benefit from faster time-to-market and ease of IP integration by making their design flows IP-XACT-enabled."

Building on the IP-XACT 1.4 specification, this next version of IP-XACT extends the IP-XACT data model to more complete description of the register data and address maps. Several small changes have been made to the schema based on the testing and feedback from the 1.4 release.

As always, the Consortium has provided automated transforms to use IP-XACT data written to previous versions. IP-XACT 1.5 is specifically targeted for hand-off to the IEEE P1685 working group for IEEE standardization. The version released to the IEEE is publicly available for informational purposes.

Silicon Motion flash controllers support Micron 34nm MLC flash

TAIPEI, TAIWAN: Silicon Motion Technology Corp., a leading fabless semiconductor company that designs, develops and markets semiconductor solutions for multimedia consumer electronics, announced that Micron Technology Inc. has validated its latest flash controllers for use with Micron's 34nm multi-level cell (MLC) flash product family.

The products include its new 16 gigabit (Gb) and 32Gb parts announced today. The validated Silicon Motion products include SM2682/SM2682LT SD controllers, SM2232/SM2234 CF controllers, SM2235/SM2242 SSD controllers, and SM3251/SM3252 USB flash drive (UFD) controllers, all of which are in mass production.

"Micron is a leader in 3x nm flash technology and we are excited that Silicon Motion has passed through Micron's validation process," said Wallace Kou, President and CEO of Silicon Motion.

"With this validation, we can offer the most advanced SD, microSD, CF, SSD and UFD controllers to support high capacity products using leading edge Micron MLC flash memory. Our controllers will allow customers to benefit from lower cost, next generation, 16Gb and 32Gb MLC 34nm NAND flash for a variety of device formats and platforms."

"Micron's new 16Gb and 32Gb MLC NAND delivers a compelling storage solution for today's consumer electronic and mobile products, offering unparalleled capacity and performance," said Brian Shirley, vice president of Micron's memory group. "Micron is pleased to have worked closely with Silicon Motion through the validation phase to ensure our mutual customers have the opportunity to design-in the latest in NAND and controller technologies."

"We believe that leading edge flash devices can accelerate the adoption of new flash applications, such as SSDs with our controllers," added Wallace Kou. "As the leader in the flash controller market, Silicon Motion will continue to work closely with all NAND flash manufacturers to ensure that our customers have access to the most advanced controllers that capitalize on next-generation technologies."

Emulex advises stockholders to take no action to revised Broadcom tender offer

COSTA MESA, USA: Emulex Corp. said that its Board of Directors, consistent with its fiduciary duties and with the assistance of its financial and legal advisors, Goldman, Sachs & Co. and Gibson, Dunn & Crutcher LLP, respectively, will review the terms of the revised tender offer from Broadcom Corp. to acquire all of the outstanding Emulex shares for $11.00 per share in cash.

Broadcom's previous offer was $9.25 per share in cash. The Emulex Board will make its recommendation to stockholders on the revised tender offer in due course. The Company urges stockholders at this time not to tender any shares into the revised offer pending the Board's recommendation.

Emulex noted that Broadcom stated in their announcement that Broadcom dropped its consent solicitation without delivering any consents and that Broadcom has also filed a notice of dismissal of its Delaware litigation against Emulex and the Emulex Board of Directors.

Emulex stockholders with any questions about the tender offer or other related matters may contact MacKenzie Partners, Inc. at 1-800-322-2885.

Elpida to get funds from government, Taiwan Memory

This is a very important news, courtesy, MarketWatch!

By Lisa Twaronite, MarketWatch
TOKYO (MarketWatch): Elpida Memory Inc. will receive 50 billion yen ($521 million), the government said Tuesday, much of it as part of Japan's new recapitalization program for struggling non-financial companies.

Japan's Ministry of Economy, Trade and Industry said Elpida will get 30 billion yen from the Development Bank of Japan by the end of August in exchange for preferred shares.

The infusion is part of a new program is aimed at supporting companies whose failure the government fears could have a broader economic impact.

"Elpida faces a very tough environment," Economy, Trade and Industry Minister Toshihiro Nikai was quoted as saying in several reports from the region. "DRAMs are widely used by major industries in our country, and securing the stable supply of them will benefit people's lives, as well as economic and industrial activities."

Taiwan Memory Co., a chipmaker set up by the island's government, plans to invest an additional 20 billion yen by the end of this fiscal year ending in March 2010, the ministry also said.

Elpida Memory Inc. President Yukio Sakamoto reportedly told a news conference Tuesday that the fund injection under the government's new aid program was the best option available for the chip maker to secure funding and remain competitive.

Last month, Japan's only maker of dynamic random access memory chips posted a group net loss of 178.8 billion yen for the fiscal year which ended in March, deeper than its 23.5 billion yen loss for fiscal 2007.

Pioneer, NEC next?
Other Japanese firms are expected to follow Elpida's move to seek funds.

Pioneer Corp., which anticipates a sixth consecutive year of losses this fiscal year, is now making preparations to apply for a public fund infusion, Japanese business daily Nikkei reported Tuesday.

NEC Electronics Corp. and Renesas Technology Corp. are also expected to consider taking action if their planned merger next April goes through as expected, the report said.

In Tokyo, Elpida shares closed up 1.4 percent, and NEC Electronics gained 4.2 percent. But Pioneer shed 1 percent.

The benchmark Nikkei 225 Average rose 1.8 percent.

Lisa Twaronite reports for MarketWatch from Tokyo.

The SDR Forum general meeting to feature FPGA Development Workshop

SAN JOSE, USA: The SDR Forum, a non-profit member consortium dedicated to promoting the success of next-generation radio technologies, announced its 64th General Meeting, to be held in San Jose, Sept. 14-17, 2009.

The meeting will feature a workshop, "Rapid FPGA Development for Wireless Applications –- IP Cores, Tools and Standards," which aims to arm communications systems engineers with the knowledge they need to implement software defined and cognitive radio systems that utilize FPGA-based processing.

Speakers at this workshop will include representatives of The MathWorks, Mercury Computer, Open Cores Protocol -– International Partnership, Objective Interface Systems, PrismTech, Synopsis and Xilinx.

Sponsored by Xilinx, this meeting represents the 64th General Meeting of the Forum, and will comprise of working sessions advancing The SDR Forum’s 2010 operations plan in support of the commercial, public safety, satellite communications and international tactical radio communities.

The meeting will feature a keynote presentation by Dean Westman, Vice President – Communications Business, Xilinx, titled “The Programmable Imperative: Multimode IS the new air interface.”

NI's USB device and sensor suite for sound, vibration apps

AUSTIN, USA: National Instruments has announced a new portable bus-powered dynamic signal acquisition (DSA) module and a suite of vibration sensors that are ideal for making high-accuracy vibration measurements required for noise, vibration and harshness (NVH) and machine condition monitoring applications.

The NI USB-4431 DSA module acquires data at rates from 1 to 102.4 kS/s, which makes it possible to obtain a wide measurement bandwidth. The combination of the USB-4431 and the new vibration sensors, which include three accelerometers, a triaxial accelerometer and an impact hammer, gives engineers and scientists a complete stimulus response system from a single vendor for seamless product integration.

The USB-4431 is a five-channel DSA module for making high-accuracy measurements from integrated electronics piezoelectric (IEPE) sensors. The module consists of four 24-bit simultaneously sampled analog input channels and one 24-bit analog output channel, which are ideal for stimulus response test systems.

The USB-4431 also works well for a wide variety of field test applications such as frequency response audio tests and suspension shaker tests due to its portability. Additionally, the module delivers 100 dB of dynamic range and incorporates software-selectable IEPE signal conditioning for accelerometers and microphones.

The new sensor suite includes three high-accuracy accelerometers and a triaxial accelerometer that are compatible with all NI DSA devices. The accelerometers have low-impedance output signals that allow for accurate signal transmission over long cables, and their small form factor makes them easy to include in a wide variety of monitoring and test systems.

The triaxial accelerometer characterizes the acceleration of an object or device being measured in all three dimensions with a single sensor to minimize cabling at the source.

Also included in the sensor suite is a modal analysis impact hammer, a device that delivers effective measurements of stimulus signals. With this highly flexible impact hammer, engineers and scientists can measure the stimulus force for a wide range of frequencies and magnitudes required for proper object characterization.

The impact hammer, triaxial accelerometer and USB-4431 combine to form a precise
structural monitoring stimulus response test system.

Engineers and scientists can get their applications up and running quickly and efficiently with the configuration-based NI Sound and Vibration Assistant software or with more than 50 ready-to-run NI LabVIEW software example code bases provided in the NI Sound and Vibration Measurement Suite.

The software suite includes a pre-built Sound and Vibration Assistant project for impact hammer response to help engineers and scientists rapidly set up a structural test application.

The Sound and Vibration Measurement Suite also features pre-built virtual instruments (VIs) for NVH and rotating machinery vibration analysis applications so engineers and scientists can quickly set up almost any sound and vibration application.

Zilog intros enhanced, low-voltage serial communications controller

SAN JOSE, USA: Zilog Inc., a supplier of application specific, embedded system-on-chip (SoC) solutions for industrial and consumer markets, has announced a new enhanced low-voltage serial communications controller (SCC) for a variety of computing applications requiring increased performance and lower power consumption.

The Zilog Z8523L Enhanced SCC (ESCC) builds on Zilog's popular and original discrete SCC, providing a low-power solution that reduces the voltage from 5 to 3.3 volts. The ESCC also features performance improvements that allow applications including computer peripherals, networking equipment and routers to experience faster data rates and increased processor bandwidth.

"Zilog has made significant improvements with our new ESCC that helps our customers bring their high-speed data applications to market quicker, reducing their total cost and extending the life of their applications," said Mike Orr, Zilog vice president and general manager, Microcontroller Business Unit.

Before developing the 3.3 volt ESCC, Zilog customers used a regulator to achieve lower voltage with the original 5 volt Zilog SCC. The Zilog 3.3 volt ESCC has deeper FIFOs and other features that significantly reduce the software overhead for each channel. This allows for more channels per system, faster data rates with more CPU bandwidth and overall lower CPU costs.

The ESCC can support multiple channel and multiple protocols that easily interface to 8/16 bit addressable non-multiplexed address/data buses. The ESCC can be configured to satisfy a wide variety of serial communications applications.

On-chip features include baud rate generators, digital PLLs and crystal oscillators to reduce external logic. Additional features may include optimized FIFOs to support high speed SDLC transfers using DMA controllers.

The ESCC handles asynchronous formats, synchronous byte-oriented protocols and synchronous bit-oriented protocols. The ESCC can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes.

The ESCC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O.

Zilog ESCC's are designed for use in multiple applications for serial communication needs. One of the key features offered by the ESCC is Extended Read Enable. Write Register values from the WR3, WR4, WR5, WR7, and WR10 can be examined in the ESCC. This feature improves system testability. It is also crucial for SCC/ESCC differentiation and allows generic software structures for all SCC/ESCC devices.

Intel Developer Forum 2009 to mix business with pleasure!

SAN FRANCISCO, USA: Intel Corp.'s largest technical conference returns to San Francisco on Sept. 22-24. Registration is now underway for the Intel Developer Forum, featuring three days of vision, learning and collaboration at Moscone Center West.

In its 12th year, IDF focuses on Intel's technology and platform roadmap directions for the next year and beyond in the areas of digital enterprise, mobility, digital home, software, manufacturing and research.

"IDF is the place to be for thousands of developers, technologists and business managers to learn where technology is going, enabling them to develop product strategies," said Mark Erwin, general manager of the event that drew more than 5,000 attendees last year in San Francisco.

"In every conference room, every corridor, every nook of the conference brilliant minds meet, collaborate and learn from one another. It's also where major announcements are made, which is one of the reasons the event is covered onsite by nearly 600 of the world's top journalists and analysts."

Intel leaders will delve into key strategies on myriad topics during all three days. CEO and President Paul Otellini will kick off the opening day keynote slate with a leadership address. Next up is Pat Gelsinger, senior vice president and general manager, Digital Enterprise Group, discussing "Intel Architecture Innovates and Integrates." Bob Baker, senior vice president and general manager, Technology and Manufacturing Group, will share insights on "Silicon Leadership: Delivering Innovation in High Volume."

Day 2 keynotes are "The Mobile Computing Revolution" by David Perlmutter, executive vice president and general manager, Mobility Group; "Developing for the Full Spectrum of Computing" by Renee James, vice president and general manager, Software and Services Group; and "The Architecture of Television Innovation," by Eric Kim, senior vice president and general manager, Digital Home Group.

The anchor keynote on Day 3, "The Future of Mobile and Immersive Computing Experiences," will be delivered by Justin Rattner, Intel senior Fellow and vice president, and Intel Labs director and chief technology officer.

A special event on Tuesday evening will be a concert by three-time Grammy Award-winning Maroon 5. One of the most successful bands to emerge this decade, Maroon 5 has more than 15 million in worldwide sales and a remarkable string of hit singles, including "Makes Me Wonder," "Wake Up Call," "Won't Go Home Without You" and the band's first Top 10 hit, "This Love." Admission to the concert is open to all IDF registrants.

Other highlights during IDF include the industry Technology Showcase, home of the latest innovations demonstrated by representatives from leading technology companies. Also returning are the popular Technology Insights, where attendees get the latest on Intel processor technologies from Intel Fellows.

Industry Insights feature industry visionaries and Intel Fellows, and Live & Uncensored (formerly Shop Talk), promises that no question is off-limits. In all, more than 125 technical sessions are planned, including interactive lecture sessions, hands-on labs and panels.

IDF Gold Sponsors to-date: Absolute Software, Cisco, Ericsson, Microsoft, Rambus, Sun Microsystems and Supermicro. Silver Sponsors are Hynix, Lenovo, Symantec and VMware.

Micron intros 34nm high-density NAND products

BOISE & FREMONT, USA: Micron Technology Inc. today announced mass production of new NAND flash memory products using its award-winning 34nm process technology.

As consumers demand increased capacity to store more music, videos, photos, and applications in ever smaller portable electronic devices, manufacturers need a storage solution that delivers on capacity, performance, and size.

Micron’s new 16- and 32-gigabit (Gb) NAND chips pair large capacity with performance, providing a compelling solution for today’s demanding portable storage requirements that are tailored to end-customer product dimensions.

The newly architected 32Gb multi-level cell (MLC) NAND chip is 17 percent smaller than Micron’s first-generation 32Gb chip. The 16Gb MLC NAND chip, at just 84mm², provides high-capacity in an ultra tiny package. Micron is also now sampling 8- and 16Gb single-level cell (SLC) NAND chips using the 34nm process.

Additionally, Lexar Media Inc., a subsidiary of Micron and a leading provider of consumer memory products for digital devices –- is taking advantage of Micron’s new 34nm NAND products by delivering a wide range of flash memory cards and USB flash drives utilizing this technology.

“Our industry-leading NAND products are opening new possibilities for some of the world’s most popular consumer electronic devices,” said Brian Shirley, vice president of Micron’s memory group.

“With our new 16- and 32Gb NAND chips in mass production, we are enabling customers to design cost-effective, high-capacity storage in their small-form factor products, using less space and fewer die. In addition, the high-speed interface is ideal in the industry’s quest to continue to increase throughput performance for SSDs.”

Both products feature an ONFI 2.1 synchronous interface that delivers transfer speeds of up to 200 megabytes per second (MB/s). In comparison, traditional SLC NAND is limited to 40 MB/s. With this improved transfer speed, the interface delivers the fastest read and write throughputs offered in today’s NAND devices.

With solid state drives (SSDs) trending toward a SATA 6 Gb/second interface, the high-speed NAND interface enables manufacturers to design products that deliver twice the throughput of today’s existing SATA 3Gb/s solutions. Customers can expect this high-speed interface designed into all future high-density Micron NAND products.

High-capacity memory cards from Lexar
Lexar Media is utilizing Micron’s high-capacity 34nm technology in its high-performance memory cards, including the new Lexar Platinum II 32GB Secure Digital High Capacity (SDHC) memory card and the Lexar 16GB microSDHC mobile memory card.

By the end of September, Micron’s new 34nm NAND will also be used in a wide range of Lexar microSD and microSDHC cards, Memory Stick Micro (M2) cards, and various capacities of Secure Digital, SDHC, CompactFlash®, and Memory Stick PRO Duo cards.

Additionally, Micron 34nm NAND will be used in Lexar’s JumpDrive USB flash drives, including JumpDrive Retrax, JumpDrive TwistTurn, JumpDrive FireFly, and JumpDrive Secure II Plus.

“By integrating the increased capacity and performance of Micron’s new 34nm NAND into Lexar’s flash memory products, we are giving our customers the ability to take full advantage of their digital cameras, phones and devices,” said Greg Rhine, vice president of sales and product marketing at Lexar Media.

“With Lexar’s cost-effective, high-capacity, and high-speed memory cards and USB flash drives, consumers can capture more pictures and videos, listen to more music, and transfer data between their devices even faster than before.”

The first Lexar memory card to feature Micron’s new 32Gb NAND chip is the new 32GB Lexar Platinum II SDHC memory card. With the ability to store up to 12 hours of high-definition (HD) video or more than 20,000 5-megapixel images, the increased capacity enables photographers to capture important events and memories with photos and HD video.

Beyond video and photography, the Lexar Platinum II 32GB SDHC memory card can be used as a convenient way to expand the available storage in today’s emerging, ultra-portable notebook computer applications, such as netbooks and mobile Internet devices (MIDs).

In addition to its high capacity, the new Lexar Platinum II SDHC card is speed-rated at 60x (Class 4), offering a minimum-sustained write speed of 9MB per second that enables photo enthusiasts to take advantage of their camera’s burst-mode setting to capture many images in rapid succession. In addition, a minimum-sustained read speed of 12MB per second ensures fast transfers of images from the card to a host computer.

Micron’s tiny 16Gb, 34nm NAND chip, which is approximately one-third the size of a keyboard key, is ideal for ultra-small, high-capacity microSD cards, such as the Lexar 16GB microSDHC mobile memory card.

The Lexar 16GB microSDHC card allows consumers to expand the capabilities of their digital devices, such as mobile phones with photo and video capture capabilities, MP3 players, and smartphones. Consumers can store up to 48,000 2-megapixel JPEG photos, 4,000 songs, or 80 hours of standard-definition video content on the Lexar 16GB microSDHC card when used in a digital device.

IBM to provide application management services to Applied Materials

ARMONK, USA: IBM Corp. has signed a five-year strategic agreement to provide Applied Materials Inc., the global leader in nanomanufacturing technology solutions, with IT application development and maintenance services.

Under the agreement, IBM will be responsible for software application development, support and deployment. It will help centralize application support and increase efficiencies for Applied by providing a stable, flexible and scalable IT platform for its worldwide operations.

"As the leading provider of equipment to manufacture semiconductors, flat panel liquid crystal displays and solar photovoltaic cells, we depend on world-class operations within our enterprise," said Ron Kifer, Group Vice President and Chief Information Officer at Applied Materials.

"Information technology is a critical enabler of our business, and we selected IBM because it has the technical capabilities and portfolio of services to meet these needs worldwide."

IBM will provide Applied with an innovative service management framework that includes: application development, diagnostic and issue resolution support, database monitoring, security and controls monitoring, performance services, batch scheduling and data interface monitoring.

"In today's economy, our clients are looking for new ways to increase their IT efficiencies, and they are looking to service providers they can count on to help balance costs and system performance requirements," said Frank Kern, IBM Global Business Services. "With IBM's capabilities in application development and through its global delivery centers, we can help Applied Materials realize its business objectives."

TI's four new processors provide unmatched connectivity options

BANGALORE, INDIA: Connected, energy-efficient designs require high levels of peripheral integration, lower heat dissipation and longer battery life.


To address this, Texas Instruments Inc. (TI) today announced four new processors -- the TMS320C6742, TMS320C6746, TMS320C6748 and OMAP-L138, respectively -- with unmatched connectivity options and fixed- and floating-point capabilities that are also the industry’s lowest power floating-point digital signal processors (DSPs).

Ramprasad Ananthaswamy, Director, Power Management Products, Texas Instruments India said: “Packed with a unique combination of application-tuned features and peripherals, these devices reduce overall system cost for a wide spectrum of products including industrial, communications, medical diagnostics and audio.”

For instance, power protection systems benefit from the OMAP-L138 device’s fixed/floating-point DSP, ARM9, Ethernet MAC (EMAC) and LCD controller for up to $14 cost reduction compared to current solutions. For applications that need high-speed data transfer and high-capacity storage, such as test and measurement, public safety radios, music effects and intelligent occupancy sensors, the processors feature a universal parallel port (uPP) and are also the first TI devices with an integrated Serial Advanced Technology Attachment (SATA).

With performance levels up to 300 MHz, these products offer the ability to manage on-chip power through dynamic voltage and frequency scaling (DVFS) and multiple power down modes.

When coupled with TI power management software and complementary analog solutions, developers can optimize their system for performance and power without having to be an energy expert. To ease and reduce development time, the new offerings are pin-for-pin compatible with each other, code compatible with all TMS320C6000 devices and complemented by a low-cost experimenter board and full-featured evaluation module (EVM).

C6742, C6746 and C6748 DSP key features and benefits:
* Lowest-cost and lowest-power C6000 processors and industry’s lowest-power floating-point DSPs with 7mW of standby power at 1.0V/25°C and 420mW total power in use case scenarios.
* Standby power up to nine times lower than existing floating-point DSP solutions on market.
* First TI processor with an integrated SATA for high-capacity data storage.
* A uPP enables high-speed connection to data converters, FPGAs or other C6742/C6746/C6748/OMAP-L138 processors.
* EMAC, multimedia card/secure digital (MMC/SD) and high-speed USB 2.0/1.1 for desktop, network or portable connectivity or storage.
* Video port interface provides the ability to input/output raw video while a LCD controller allows developers to easily connect video graphics array (VGA) resolution displays.
* Multiple operating points facilitated through DVFS, powering off unused peripherals and selectable I/O voltages enable portability and reduce heat dissipation in products.
* Complementary TI TPS65070 power management device implements all sequence and default options as well as supports the devices’ power modes.
* C674x core up to 300MHz provides floating-point operations for high-precision and wide dynamic range as well as fixed-point operations for higher performance.
* Pin-for-pin compatibility (C6742, C6746, C6748 and OMAP-L138) enables customer to expand their entire product portfolio using the same hardware and software platform
128 KB to 448 KB on-chip memory to reduce external memory access and power usage.

OMAP-L138 processor features and benefits:
* Dual-core processor that builds on the C6748 DSP with a 300 MHz ARM9 gives developers the flexibility to add intuitive human machine interfaces, touch screens or networking capability to their applications.
* ARM9 allows developers to implement high-level operating systems, such as Linux
Windows® Embedded CE and Integrity support is expected in 4Q09.
* Low power usage with 440mW total power and 15mW in standby mode in use case scenarios.

Development tools for varying levels of expertise:
* A community-supported $149 experimenter board is available from Logic, the designer and manufacturer. The board features the OMAP-L138 system-on-module (SOM), 64MB mDDR, open source Linux, DSP/BIOS drivers and can be used to develop on any of the four devices.
* An OMAP-L138/C6748 EVM from TI is available for those that need full peripheral access and TI support. The EVM builds on the experimenter board with an extra C6748 SOM, double the memory (128 MB mDDR) and full support for connectivity peripherals.
* An OMAP-L138 (SOM) is a production-ready solution with 128 MB mDDR, power management and Ethernet PHY. It is available for less than $99 @ 10k EAU from Logic.

New mag for organic semiconductor and organic electronics industry

CAMBRIDGE, UK: cintelliq Ltd, a leading provider of technology consulting and information services to the organic semiconductor industry, announced the launch of its latest FREE publication The OSADirect Magazine.

Published bi-monthly The OSADirect Magazine covers the technical and commercial developments of the rapidly growing organic semiconductor and organic electronics industries, as well as electronics devices that incorporate carbon nanotubes, fullerenes and graphene.

The launch of The OSADirect Magazine has grown out of the success of the weekly OSA Direct newsletter that been continuously published since 2003. A key reason for the success of OSA Direct has been its brevity.

However, as the industry is now moving towards early commercialisation it is timely that a dedicated publication that includes more in-depth articles, reviews and analysis is available for the industry.

Subscribers to The OSADirect Magazine benefit from receiving the latest market news, technical news, financial news, conference reports, contributions from key players in the industry as well as in-depth analysis of OLEDs, OLED lighting, organic transistors and organic photovoltaics for a growing range of end-user applications including for example displays, lighting, solar cells, RFID, active-matrix backplanes, and e-Readers.

The readership includes CEOs, CTO, as well senior commercial and technical personnel from the leading players across the whole supply-chains, from materials suppliers all the way through to device developers and end-users.

Each issue of The OSADirect Magazine will have a specific editorial focus in addition to news. In the launch issue this editorial focus is OLED lighting with a contribution from Philips Lighting, a conference report from the 1st FineTech OLED Lighting Technology Conference, Government investments in OLED lighting projects, and analysis of OLED lighting patents.

The next issue of The OSADirect Magazine will be dedicated to organic photovoltaics.

Craig Cruickshank, cintelliq CEO, said, "Since launching the original OSADirect free weekly newsletter in 2003 the organic semiconductor industry has grown tremendously and with the industry now moving toward early commercialisation, it is timely that a dedicated magazine is available for the industry.”

He added, “cintelliq has established itself as leading source of industry information, and The OSADirect Magazine is a valuable resource for subscribers to keep up to date with the latest industry developments and trends.”

SMIC achieves silicon success with high performance 45nm process

SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. announced the successful completion of its first 45-nanometer high performance (GP, generic process with high performance) yield lot.

SMIC's high-speed, high performance 45nm GP technology integrates a silicon germanium stress module into the design, allowing the device to run faster, making it ideal for a number of applications, including system-on-chip, graphics and network processors, telecommunications and wireless consumer products, and serves as a technology platform for the fast growing China market.

The 45nm GP technology bookends with SMIC's silicon success on its 45nm low power (LP) technology, which is suitable for mobile devices that put a premium on low power consumption. SMIC signed an agreement with International Business Machines (IBM) to license its low-power and high-performance bulk CMOS technologies in December 2007. The GP technology transfer was completed in March 2009.

"I'm delighted with the progress of SMIC's 45nm project team, which continues to meet rigorous deadlines, and we appreciate the excellent support from IBM throughout this progress," said Dr. Robert Tsu, SMIC's 45nm project leader and Associate Vice President of Logic Technology. "Integrating the silicon germanium process and achieving a well-yielded test chip from the very first yield lot is a significant technical accomplishment, and these accomplishments allow SMIC to provide a highly manufacturable technology to our customers."

SMIC's 45nm GP technology is supported by a proven design-in SPICE model and in-house design IP capability that enables customers to begin prototype product design and plan for early time-to-market. In June, SMIC announced the adoption of new SPICE model software for the design and verification of 45nm IP blocks, I/O circuitry, and standard cell characterization flows.

As the company's 65nm low-power technology development cycle comes to a successful close, with a recently completed IP portfolio, multiple customer product qualification, and a ramping up of production, efforts have focused on 45nm. The readiness of SMIC's 45nm LP and GP technologies for design-in allows customers to enter a premium-value market.

"We are very excited and encouraged by the completion of our first 45nm high performance yield lot, another important signpost in SMIC's strategic plan," said Dr. Richard Chang, SMIC's President and CEO.

"It verifies the IBM-licensed technology, validates our strategic decision to invest in advanced logic technologies, and enhances SMIC's position as the advanced logic technology leader in China. This 45nm GP process is a proven, robust, high yielding, and high performance technology that we anticipate can not only deliver better performance, reliability, and cost to our valued customers, but also help SMIC become even more competitive in China and worldwide."

Broadcom raises Emulex offer to $11.00 per share

IRVINE, USA: Broadcom Corp. announced that it raised its tender offer for all of the currently outstanding shares of common stock (including the associated preferred stock purchase rights) of Emulex Corp. from $9.25 to $11.00 per share in cash, representing a total equity value of approximately $912 million.

As required by law, Broadcom will extend its tender offer for an additional 10 business days, until midnight New York City time, July 14, 2009.

This is the best offer Broadcom intends to make, reflecting Broadcom's assessment of the publicly available information on Emulex and the value Broadcom anticipates to itself from an expedited transaction.

The offer represents a premium of 66 percent to Emulex's closing stock price on April 20, 2009, the day before Broadcom announced its initial offer; of 93 percent to the average closing price for the 30 trading days before Broadcom's initial offer; of approximately 149 percent to Enterprise Value on the day before Broadcom's initial offer; of 69 percent to the analysts' median 12-month price target for Emulex on the day before Broadcom's initial offer.

Broadcom recognizes that, in the absence of its offer, Emulex's share price would have continued to fluctuate in the two months since Broadcom's initial offer. Had the Emulex stock traded in line with the stock of its closest peer, QLogic Corp. (up 7.6 percent since April 20, 2009), it would be $7.11 today. Broadcom's revised offer represents a premium to this implied current share price of 55 percent.

eInfochips announces host of VMM-enabled verification IPs for Synopsys

AHMEDABAD, INDIA: eInfochips Ltd., a leading design services company today announced the availability of Verification Methodology Manual (VMM)-enabled MIPI CSI-2 (Camera Serial Interface), DSI (Display Serial Interface), HSI (High Speed Synchronous Interface) and SDIO Verification IP (VIP).

The eInfochips VIP has also been added to the Synopsys DesignWare Verification IP Alliance Program. The Alliance program gives designers access to a broader range of VMM-enabled verification IP, which complements DesignWare Verification IP portfolio. Synopsys selected and qualified eInfochips for the Alliance program because of its extensive experience in verification, VMM methodology and verification IP development.

“eInfochips has been developing verification IP for many years and has seen an increasing demand for VMM-enabled verification IP for MIPI standards,” said Sribash Dey, VP of Sales at eInfochips. “By working closely with Synopsys to develop VIP that is in accordance with Synopsys’ guidelines and VMM rating tool, our mutual customers can have access to a wider range of VMM-enabled verification IP that helps accelerate their verification process.”

“The addition of eInfoChips’ MIPI and SDIO VIP to the DesignWare VIP Alliance Program further expands the broad range of VMM-enabled verification IP that is complementary to the DesignWare portfolio” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “With eInfochip’s extensive experience in VMM-enabled verification IP, designers can have confidence that the verification IP can be easily integrated into System-Verilog verification environments, helping to speed testbench development efforts.”

eInfochips' VMM-enabled MIPI CSI-2, DSI and HSI, and SDIO VIP products are based on the layered architecture of object oriented programming that allows coverage-driven verification suitable for verifying transmitter and receiver with either of them as the design-under-test (DUT).

MIPI CSI-2 VMM-enabled verification IP
eInfochips’ VMM-enabled MIPI CSI-2 VIP is compliant to the CSI-2 MIPI Specification version 1.0 and draft MIPI Alliance Standard for D-PHY Version 0.85.00. MIPI CSI-2 is an interface between a digital imaging module such as a host processor and image sensor peripheral such as a camera.

The VIP for the MIPI CSI-2 interface can be configured as a Transmitter, Receiver or Monitor. The four-channel VMM-enabled MIPI CSI-2 VIP has fully configurable short and long packets and supports RGB, YUV and RAW long packet data types and short pack synchronization.

The VIP supports directed/constrained/fully random testing mode, monitors and checkers for protocol violations, coverage report generation while allowing configurable transaction generation for each device model.

MIPI DSI VMM-enabled verification IP
eInfochips’ VMM-enabled MIPI DSI VIP is compliant to the DSI MIPI Specification for Version 1.00 and draft MIPI Alliance Standard for D-PHY Version 0.85.00.

MIPI DSI is an interface between a digital imaging module such as a host processor and display peripheral such as an LCD. The MIPI DSI VIP can be configured as a Transmitter, Receiver or Monitor and allows system level verification.

It is a highly configurable, SystemVerilog verification IP that supports four virtual channels, RGB color format for 16bit, 18bit and 24 bit, DCS read/write commands & generic write commands, interleaved and normal frames, bidirectional data transfer and PPI control interface.

The VIP supports fully configurable fields of short and long packets, directed, constrained and fully random testing, coverage report generation and command mode of operation.

MIPI HSI VMM-enabled verification IP
eInfochips’ MIPI HSI VMM-enabled VIP is compliant with the version 1.01.00 specification. MIPI HSI is an interface between an applications processor and cellular modem. The MIPI HSI VIP can be used for system level verification of DUT MIPI HSI transmitter and/or receiver and for functional coverage generation.

The highly configurable, VMM-enabled SystemVerilog verification component supports synchronized/pipelined/receiver data flows and stream/frame transmission modes. Other features of MIPI HSI VIP are error injection, functional coverage, random as well as user-defined configuration and run-time configurability.

SDIO VMM-enabled verification IP
eInfochips’ VMM-enabled SDIO HOST VIP allows coverage-driven verification and can be configured as IO-aware or non IO-aware to verify SDIO card, SD memory card, SD Combo card and SD Multimedia Card (MMC).

The VIP is compliant to the SD Host Specification 1.0, SD Specification 1.10 and 2.00 and to the SDIO Specification 1.2. It offers support for single slot operation, card detection, re-initialization of combo card, 1/4/8 bit SD bus mode and SPI bus mode, low/full/high speed, stream transfer and direct command during data transfer.

The VIP also facilitates functional coverage, card suspend/resume/lock/unlock operations, protocol and transaction level checking and plug-and-play operations.

Deliverables
Deliverables include verification IP encrypted code, sample test bench and test cases, user guide and release notes. eInfochips provides regular product updates and technical support. MIPI CSI-2, HSI, DSI and SDIO VMM-enabled VIP products are now available.

Future Horizons signs up Israeli representative

LONDON, UK: Future Horizons, the global semiconductor industry analyst house, has entered the Israeli market by signing up Amir Ben-Artzi as a representative.

Formerly a journalist with EE Times and IDG, editor of several technology magazines and a public relations supervisor for companies such as Intel, Ben-Artzi brings an impressive track record within the semiconductor industry to the world’s leading independent semiconductor analyst house.

“The Israeli market offers incredible potential for technology companies and is fast becoming a centre of innovation for our industry,” said Malcolm Penn, Chairman and CEO, Future Horizons. “We have known Amir for many years now from his days as a journalist, and his track record and connections in and outside of Israel make him the perfect representative to help bring Future Horizons to this new market.”

Ben-Artzi, the founder and head of Amir Ben-Artzi Content & Media, brings over 15 years of experience in the industry to Future Horizons. Both organisations are expanding into new areas and offer each other a multitude of benefits and contacts.

Ben-Artzi will represent Future Horizons in Israel and help promote the upcoming International Electronics Forum alongside the Start Up Service and consulting opportunities.

“With so many new and existing companies in Israel, Future Horizons’ upcoming International Electronics Forum and Start Up Service are just two of the services that will really appeal to this market,” said Ben-Artzi. “Future Horizons is one of the most respected analyst houses in the industry, and Malcolm’s impartial and honest analysis will be of real benefit to many of the technology companies here.”

Future Horizons’ International Electronics Forum will be held in Geneva, Switzerland, from Wednesday 30 September-Friday 2 October 2009. With high-level speakers and a broad pool of delegates, it maximises productivity and delegate ROI.

It is specifically designed to foster networking opportunities across a broad pool of disciplines in a condensed, value-added period. Such is the established reputation of the Forum, the vast majority of speakers and delegates stay for the full duration of the meeting.

Cadence, Xilinx simplify SoC development for FPGA targeted design platforms

SAN JOSE, USA: Cadence Design Systems Inc. has teamed with Xilinx to enable delivery of encrypted simulation models of Xilinx intellectual property (IP) in the latest 11.2 release of the Xilinx ISE Design Suite.

The result is an expanded library of design IP and complementary simulation models supported by the Cadence Incisive functional verification platform for the new Xilinx Base Targeted Design Platform.

Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.

Xilinx Targeted Design Platforms enable embedded, digital signal processing (DSP) and hardware designers alike to develop FPGA-based systems on chip (SoCs) faster with access to a wide array of silicon devices supported by open standards, common design flows, reusable IP, development tools, and run-time platforms.

Using the high-performance IEEE-standard encryption donated by Cadence, Xilinx is now able to deliver Xilinx SecureIP models to speed development of designs targeting its latest Virtex-6 FPGAs and Spartan-6 FPGAs.

“Our customers have been building larger and more complex FPGA-based SoCs, which require more advanced verification techniques,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.

“Working closely with Cadence, we are able to deploy our SecureIP models using the new IEEE encryption with users gaining 2X performance improvements in simulation. When used in conjunction with the OVM, this enables greater verification efficiency throughout the FPGA development ecosystem.”

“Advances in technology announced by Xilinx and Cadence can translate into real time-to-market and quality boosts for our mutual customers,” said Michal Siwinski, marketing group director of Enterprise Verification at Cadence.

“Xilinx Targeted Design Platforms enable rapid creation of SoCs that scale to the sweet spot for both the OVM and the Cadence Incisive functional verification, helping customers to reduce overall project costs and risks.”

SMSC intros I/O port expander and DTCP co-processor for MOST networks

HAUPPAUGE, USA: SMSC, a leading semiconductor company that provides smart mixed-signal Connectivity solutions, announced the OS85650 I/O companion chip for MOST intelligent network interface controllers (INICs).

With its multiple interfaces, powerful routing engine and the DTCP co-processor, the OS85650 can be used for various audio and video applications such as Head Units, Rear Seat Entertainment, Amplifiers, TV-Tuners and Video Displays.

The OS85650 works together with SMSC INICs for all MOST speed grades (MOST25, MOST50 and MOST150) and can replace many of today’s expensive FPGA solutions.

“With its expanded communication ports, this companion chip allows the INIC family to stay cost optimized in providing minimal application interfaces at a low pin count,” said Stefan Lux, Product Marketing Manager for SMSC’s Automotive group. “Together with the INIC, the OS85650 offers a complete solution for network applications, including data exchange on MOST networks.”

The primary function of the OS85650 is to route data streams simultaneously between industry standard application I/O interfaces, including MediaLB (3-Pin and 6-Pin), HBI, TSI, SPI and I²S. It is the first MediaLB 6-Pin device that supports all features of the MOST150 multimedia network.

Together with the 16 bit parallel Host Bus Interface (HBI), it enables a high-speed connection between the INIC150 and multiple External Host Controllers (EHCs) with over 300Mbit/s. It is also possible to use the OS85650 as a bridge between MediaLB 6-Pin and MediaLB 3-Pin devices.

The high-performance routing engine operates at an internal speed up to 1.5 GBit/s. It is able to route on top of the standard MOST network communication, Ethernet IP packets, multiple MPEG-TS and several high quality 7.1 audio streams.

The Digital Transmission Content Protection (DTCP) co-processor autonomously encrypts and decrypts up to eight multiple synchronous and isochronous data channels routed through the device. It includes full AKE functionality and supports both M6 and AES-128 cipher engines according to DTCP for MOST and DTCP-IP. This content protection is required for high quality audio and video content, like DVD, Blu-ray Disc and HD-Broadcasting Services.

Samsung intros 45nm application processor for next gen CE devices

SEOUL, KOREA: Samsung Electronics Co. Ltd announced the latest in its popular, ARM11 series of application processors, the S5P6440. Designed using Samsung's advanced 45nm low power CMOS process technology, the S5P6440 offers a low power, high performance, and cost effective solution for consumer electronic (CE) products such as personal navigation devices (PND).

"Today's ultra-competitive consumer electronics market demands rapid performance upgrades and effective cost reduction to continue its expansion," said Dr. Kwang-hyun Kim, Senior VP of Sales and Marketing at Samsung Electronics' System LSI division.

"Our S5P6440 application processor is specifically designed with those objectives in mind to offer substantial improvements in CPU performance at low power, high quality graphics capability, and lower system BOM cost. CE device manufacturers using S5P6440 can offer exciting new products such as next generation PND to the market in a timely manner."

Samsung's S5P6440 is based on an ARM1176 CPU core which runs at either 533 MHz or 667MHz clock speed. The CPU core and all on-chip hardware accelerators and peripheral interfaces are connected through a 64-bit AXI bus running at 166MHz, allowing ample input/output bandwidth for handling the multiprocessing requirements in real-life applications.

The S5P6440 features 2D graphics acceleration hardware that is compliant with the OpenVG application programming interface (API) standard. The OpenVG API standard enables advanced graphics functions such as alpha blending for transparency effects, anti-aliasing for sharper graphics, and vector graphics support for scaling without loss of image quality. Utilizing this graphical capability, devices implemented with the S5P6440 can offer a vivid graphical user interface that greatly enhances the user experience.

To lower the system BOM cost and ease the design complexity, the S5P6440 incorporated various interface hardware IP. An advanced NAND error correction hardware is included to support current and next generation MLC NAND flash devices which offer higher storage density at a lower cost.

The S5P6440 also integrated a DRAM memory controller that supports both mobile DDR (mDDR) as well as the lower cost DDR2 memory chips, allowing device manufacturer's different choices of storage device types to meet different market segments' requirements.

In addition, the S5P6440 integrated a mobile industry processor interface (MIPI) display serial interface (DSI) for advanced graphics and display capabilities at low power. The MIPI DSI interface is valuable to customers wanting to reduce the complexity of the display interface by reducing the number of pins, which has benefits in terms of design simplicity and cost.

MIPI DSI also uses a differential signal which substantially reduces EMI issues. These advantages are increasingly important for mainstream connected CE products where noise interference among electronic components in within a product can adversely affect the product's performance.

Samsung's new S5P6440 application processor supports all major high-level operation systems including WinCE and Linux. This allows OEMs and PND manufacturers to differentiate their products through a rich, easy-to-use, customizable user interface, as well as robust, flexible application architecture.

The S5P6440 application processor is sampling to key customers now and is scheduled for volume shipment in the third quarter of this year. The chip is housed in a 13x13 FBGA package with a ball pitch of 0.65mm.

Europe makes strides on sustainable semiconductor manufacturing

GUILDFORD, ENGLAND:Pioneering the European electronics industry’s efforts for sustainable manufacturing of semiconductors, Linde Gases, a division of The Linde Group, has installed Europe’s first CE-marked on-site electronics grade fluorine (F2) generator at STMicroelectronics’ Crolles 300mm wafer fabrication plant in France.

As part of STMicroelectronics’ initiative to lower the environmental impact of producing semiconductors, high-pressure cylinder F2 has been replaced by two new Linde Generation-F on-site fluorine generators –- providing a low pressure, fully redundant supply of high purity F2 and eliminating the need to transport to and keep cylinders on site.

The Linde fluorine generators and ancillary equipment combine proven technology with intrinsically safe design to provide STMicroelectronics an on-demand, safe and highly reliable source of pure F2 for Chemical Vapour Deposition (CVD) chamber cleaning.

One cylinder of hydrogen fluoride (used as the source material for the on-site generator) provides the same amount of F2 to the fab as 100 high pressure F2 cylinders – significantly reducing maintenance workload, while the very low system pressure provides much greater safety for all STMicroelectronics engineers.

“As operators of thermal CVD furnaces look to optimize costs and minimize risk through stricter safety requirements, Linde is seeing a quicker pace of adoption for on-site generated fluorine,” said Greg Shuttleworth, Semiconductor Product Manager for Linde Gases Division. “We are also seeing increasing interest in using F2 as an alternative to NF3 for the cleaning of Plasma-Enhanced CVD chambers due to concerns over the very high global warming potential of NF3 and imminent legislation that could restrict its use.”

“The installation of Europe’s first on-site fluorine generators at our Crolles wafer fabrication plant is testament to STMicroelectronics’ commitment to increasing safety and improving our eco-footprint,” said David Ferrand, Director of Facilities at the Crolles 200 and Crolles 300 fabs. “We have directly reduced our carbon footprint at Crolles 300mm by eliminating cylinder deliveries. We are excited by the potential for even greater environmental efficiency by using the generation capacity in other cleaning applications.”

Previously, every cylinder change was an opportunity for contamination of the system, but now the STMicroelectronics Crolles 300mm facility has much greater reliability of gas box components by eliminating these frequent changes. There is also less hazardous waste as there is no need to purge cylinders to ensure they are completely empty before changing, increasing savings and reducing the load on ST's abatement systems.

The Linde Generation-F on-site fluorine generator has been through extensive third-party safety evaluations and can now add the CE Mark to the SEMI S2 certificate among its list of national and industry recognised safety standards.

In addition to the generators themselves, Linde’s ancillary buffer and abatement systems, which safely deliver variable amounts of fluorine, have also been CE-marked and SEMI S2 certified. Including those at STMicroelectronics, Linde has supplied and operates nearly 30 Generation-F systems worldwide to meet the semiconductor, display and photovoltaic industries’ chamber cleaning needs.

STMicroelectronics' programs to reduce the use of energy, water and chemicals at all sites are the foundation of its longstanding eco-efficiency approach to environmental stewardship. STMicroelectronics considers the management of the chemicals it uses, along with climate change, as the most important environmental issues, and has been reducing chemical consumption by more than five percent a year, on average, since 1998.

TSMC enhances 0.13-micron family

HSINCHU, TAIWAN: Taiwan Semiconductor Manufacturing Co. Ltd has released an enhanced version of its 0.13-micron process to benefit customers' cost and competition and to enable the integration of power management functions.

The 0.13-micron/0.11-micron family now includes a slim standard cell, SRAM and I/O with substantial area reduction and the 0.13-micron process also adopts LD-MOS (5V~20V) on RF platforms to enable analog and power management applications. The slim platform is available in the third quarter this year while the LD-MOS on RF platforms will be available in Q4 this year.

To meet the ever shrinking requirements for basic consumer and RF applications, the slim platform I/O area achieves a 30% reduction and SRAM bit cells demonstrate a 25% reduction when compared with traditional offerings. Furthermore, a 0.13-micron LD-MOS device built upon a RF platform enables SOC designs with power management functionality.

"This is another example of how TSMC is committed to enabling more efficient SoC design of wireless, consumer and communications devices using 0.13-micron process technology," said Dr. Simon Wang, senior director of Advanced Technology Business Division. "The result of these enhancements will spawn the next generation of innovation," he said.

TSMC's investment in R&D for technology and IP portfolios within the 0.13-micron/0.11-micron family now delivers a true 5V with Copper interconnect for the integration of analog, high-speed DSP, power management and watt-scale class-D amplification.

Along with new features development for system-on-chip design, TSMC also offers a shrunken path to enhance customer's competitiveness including sub-node and slim technology platform.

Chinese Academy of Sciences selects Vivante as GPU partner for netbooks

SUNNYVALE, USA: Vivante Corp. announced a collaborative relationship with the Institute of Computing Technology of the Chinese Academy of Sciences (ICT).

This long-term, development partnership will enable ICT and Vivante to integrate their respective CPU and GPU designs into a cost-efficient, low-power SoC and advance the state-of-the-art in netbook technology for the next generation.

ICT, which specializes in comprehensive research into computer science and technology in China, successfully produced China's first general-purpose digital computer and is an R&D base for high-performance, low-power computer technology in China. ICT research focuses on strategic, advanced, and fundamental contributions toward industry innovation, national needs, and market demands.

"As we look toward making netbooks both more capable and more accessible, we find Vivante GPUs to be the perfect solution for small size and low power while providing robust, fully featured graphics and fast performance," said Dr. Weiwu Hu, chief architect of the ICT's CPU division.

Adds Wei-Jin Dai, President and CEO of Vivante: "Our ability to deliver the highest performing GPU per square millimeter and per milliwatt across the spectrum of mobile computing, handheld, and home entertainment device requirements is once again validated by ICT selecting a Vivante GPU design.

"The Vivante ScalarMorphic GPU architecture flexes and scales to address a wide range of price/performance requirements and silicon budgets. We look forward to ongoing collaboration with ICT, as we apply leading edge Vivante technology to power next generation wired and wireless embedded applications in new and interesting ways."

NI intros PXI Express 2.53 GHz dual-core controller

AUSTIN, USA: National Instruments has introduced the NI PXIe-8108 high-performance embedded controller, which features an Intel Core 2 Duo T9400 processor and is designed to significantly reduce test times for PXI Express -- and CompactPCI Express-based automated test systems.

Engineers can use this 3U embedded controller in any PXI Express chassis to create a compact, high-performance PC-based platform for many test, measurement and control applications. With its 2.53GHz dual-core processor, 800MHz DDR2 memory and 1GB/s total system bandwidth, the NI PXIe-8108 is ideal for advanced RF and wireless test applications, high-throughput data acquisition systems and other applications that require intensive analysis, signal or image processing.

The NI PXIe-8108 optimizes RF and wireless test applications because measurement speed is related to the computational performance of the test system's controller. The advanced operation of the NI PXIe-8108 controller helps engineers maximize their controller investments by delivering up to a 25 percent performance improvement over similar systems based on previous-generation NI embedded controllers.

This results in significantly reduced RF and wireless test times including wireless local area network (WLAN) tests. For example, an NI WLAN Test System that incorporates the NI PXIe-8108 can deliver measurement times up to 10X faster than traditional WLAN instruments in WLAN protocol testing. Using the NI PXIe-8108, NI also has achieved similar test time reductions with other RF and wireless protocols including WiMAX, GPS, ZigBee and RFID.

NI LabVIEW graphical system design software, a development environment that inherently supports multithreaded applications, can maximize the use of the Intel Core2 Duo T9400 processor's dual cores in the NI PXIe-8108 to separate tasks into individual threads and simultaneously execute those threads. This function helps engineers take advantage of the processor's computational ability to optimize processing load and reduce test times.

Building on standard PXI industry specifications, a PXI Express system incorporating an NI PXIe-8108 embedded controller provides additional timing and synchronization features including a 100 MHz differential system clock, differential signaling and differential star triggers.

By using differential clocking and synchronization, PXI Express systems benefit from increased noise immunity for instrumentation clocks and the ability to transmit at higher frequency rates. With these features, PXI embedded controllers from National Instruments deliver advanced performance, longevity, reliability and fast system recovery.

Engineers already using PXI-based test systems easily can upgrade their embedded controllers to take advantage of the higher-performance NI PXIe-8108. Engineers using non-PXI systems can experience greater performance improvements by transitioning to a PXI solution based on the NI PXIe-8108 embedded controller.

MEMS markets on the rebound!

NEW TRIPOLI, USA: The MEMS device market is faring much better than the overall semiconductor industry but, the MEMS processing equipment market is suffering the same fate as the semiconductor equipment market, according to the report: The Global MEMS Device, Equipment, and Materials Markets: Forecasts and Strategies for Vendors and Foundries, recently published by The Information Network.

MEMS devices cover a broad spectrum of products such as accelerometers, digital mirror displays, gyroscopes, micro fluidic devices, microphones, and pressure sensors.

Since they are such a diverse lot, the have fared better than the overall semiconductor industry. The semiconductor industry declined 2.8 percent in 2008 and is projected to drop another 21.6 percent in 2009. The MEMS device market, in contrast, grew 1.2 percent in 2008 and is projected to increase 1.7 percent in 2009, according to the report.

"The MEMS equipment market dropped 37.5 percent in 2008 and we project a further drop of 31.2 percent in 2009, decreases similar to the 32.5 percent drop in 2008 and our projected 41 percent drop in 2009 for semiconductor equipment," noted Dr. Robert Castellano, president of The Information Network.

“Fortunately, the MEMS equipment market started to rebound in Q2, while we don’t see an uptick in the semiconductor equipment market until mid-Q3,” he added.

Nemotek announces new wafer-level optics for portable apps

MOROCCO, AFRICA: Nemotek Technologie, a manufacturer of customized wafer-level cameras for portable applications, today announced its Wafer-Level Optics (WLO) solutions are fully qualified and now available to customers.

Producing thousands of lenses simultaneously on a single wafer, Nemotek Technologie streamlines the manufacturing process delivering a more cost effective and miniaturized wafer level based on reflow compatible materials.

The reflow compatible materials are used to build the optical elements of the camera module, which are efficiently mounted directly to a board for camera phone or other mobile device assembly. Since this is the same solder reflow process used for assembling other electronics, customers save time by using the same procedure throughout the production cycle.

Nemotek Technologie enables customers to save costs with less components and manual processes ensuring higher quality at affordable prices. A fixed focus optics feature also eliminates the high costs of manual focus adjustments present in other non-wafer offerings.

To provide high performing quality products, Nemotek Technologie successfully completed a series of internal tests and qualifications for its wafer-level lenses. Several of the stress tests included a reflow test to verify all the materials used to build the lenses are reflow compatible. Other qualifications included industry-level high temperature and solar radiation tests. All the completed tests were in compliance with the Standard Mobile Imaging Architecture (SMIA).

“With the completion of several stringent tests for our wafer-level lenses, we believe our products are now of the highest quality at less cost while featuring a superior manufacturing process than other offerings,” said Jacky Perdrigeat, CEO of Nemotek Technologie. “The market is ready for wafer-level technology and we are pleased to be one of the first to manufacture these high-demand wafer offerings.”

Nemotek Technologie’s 10,000 m2 facility which includes a certified Class 10 clean room is the first in Africa located in the Rabat Technopolis Park, a hub for technology development in Morocco. In this facility will be produced high quality, low defect wafer-level solutions.

Virage Logic joins Power.org community

PISCATAWAY, USA: Power.org, the organization that promotes and develops standards for Power Architecture technology, today announced that Virage Logic Corp., the semiconductor industry's trusted IP partner, has joined Power.org as a participant member.

Virage Logic provides an extensive range of semiconductor IP that removes the traditional bottleneck in processor design -- access to embedded memories and silicon implementation -- speeding time-to-market and helping minimize design costs.

"The strength of a processor is dependent on its peripherals and with Virage Logic's production-proven, advanced interface IP solutions, PowerPC-based designs can leverage the critical IP required for successful SoC designs," said Power.org CTO, Kaveh Massoudian.

"The company's technology and expertise will provide a valuable asset to the Power Architecture ecosystem, making Power Architecture technology available to the mass market and to the mainstream fabless semiconductor market."

Recently, Virage Logic announced an agreement with IBM designating the company as an IBM PowerPC Design Center, granting it the rights to license and distribute IBM's PowerPC processor and peripheral cores when combined with Virage Logic's broad portfolio of semiconductor IP.

"Our participation in Power.org allows us to broaden the portfolio of highly differentiated silicon-proven IP available to the Power.org community," said Dr. Yankin Tanurhan, vice president and general manager, non-volatile memory (NVM) solutions, Virage Logic. "We look forward to working closely with members of the organization to drive innovation while helping them achieve their cost, performance and time-to-market goals."

Mentor extends Catapult C with support for control logic

WILSONVILLE, USA: Mentor Graphics Corp. announced that the Catapult C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS).

This breakthrough technology allows designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. Extending the Catapult C tool’s capabilities to full-chip high-level synthesis is critical due to the rapid growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.

Control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool unifies these two domains, allowing users to describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++.

At the heart of this innovation is a new synthesizable C++ construct, which allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation. This pivotal mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks.

The result is a coding style familiar to hardware designers, letting users easily express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.

The synthesis process is complemented by a patent-pending and fully automated verification flow which for the first time lets users validate the detailed RTL-level block interactions at the C level.

Tight integration between verification and synthesis has proved a necessity to realizing the full potential of HLS. A common pitfall found with other HLS tools is developing high-level synthesis in isolation, which results in overly complex verification of the RTL output.

"Our digital broadcasting ICs typically consist of a complex mix of compute intensive algorithmic units and control dominated blocks," said Professor Schlicht, Head of Department, Fraunhofer Institute for Integrated Circuits.

"The new Catapult extensions for control-logic synthesis provide us with the capability to develop an increasing portion of the overall system using high-level synthesis from C++. This allows us to extend our C++ based implementation flow beyond the pure signal processing blocks."

In addition to support for control logic, the Catapult C Synthesis tool has added innovative technology for low power design by automating two prevailing design techniques: multi-level clock gating and interfacing to dynamic power and clock management units.

The Catapult C tool will analyze deep cones of logic to find gateable clocks, an otherwise error-prone and manual task typically done by backend low power experts.
This new and unique optimization delivers near 100% perfect clock gating by operating at the flop level, maximizing power savings by locally inferring the gating logic surrounding the targeted registers.

To help further reduce power, the Catapult C Synthesis tool also exports real-time information on the state of all system blocks. This information is relayed to power management units leveraging dynamic frequency and voltage scaling heuristics to achieve system-wide power savings.

As expected, dynamic power savings is design and test vector dependent; measurements on more than 300 customer designs showed improvements ranging from 10 percent to 90 percent, with an average improvement of 40 percent.

"The control logic extensions of Catapult C now let us develop a larger part of our systems with HLS," said Emmanuel Liegeon, Deputy Manager of Digital ASIC & FPGA Design Group, Thales Alenia Space. "As we develop more and more of the system in HLS, it becomes paramount to get power right. The latest enhancements in Catapult C for low power are delivering the optimizations we need."

Catapult C
The Catapult C Synthesis tool is the first product to automatically generate control and algorithmic RTL multi-block designs from a pure ANSI C++ source where both the core algorithm and interface are untimed.

This productivity improvement gives designers time and freedom to automatically perform detailed design exploration of different micro-architectural options and interface scenarios to quickly achieve fully optimized hardware designs.

The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000.

IDT completes acquisition of Tundra Semiconductor

SAN JOSE, USA: IDT (Integrated Device Technology Inc.), a leading provider of essential mixed signal semiconductor solutions that enrich the digital media experience, today announced the closing of its acquisition of all of the shares of Tundra Semiconductor Corp. for aggregate cash consideration of approximately CDN $120.8 million.

The Tundra acquisition is expected to strengthen the IDT product portfolio of serial switching and bridging using PCI Express, Rapid IO and VME interconnect standards. Additionally, the Tundra technology, combined with the IDT mixed signal product portfolio and channel capabilities, is intended to further reinforce the IDT leadership in interconnect solutions for the communication, computing and embedded segments.

“Tundra is a great company, bringing a wealth of technologies and capabilities to IDT that are complementary to our existing product portfolios for RapidIO and PCI Express. We believe that this strategic combination will provide customers with a broader product offering as well as improved service, support and a future roadmap for serial connectivity,” said Dr. Ted Tewksbury, president and CEO of IDT.

“In addition, we currently project that this acquisition will be financially accretive to IDT’s non-GAAP EPS in the second full fiscal quarter of IDT combined operations.”

Altera announces Cyclone III LS FPGAs

SAN JOSE, USA: Expanding its leadership position in low-power solutions, Altera Corp. today announced a new low-power FPGA family with security features.

The Altera Cyclone III LS FPGAs offer the highest logic, memory, and DSP density per board area. These devices are the lowest power FPGAs at less than 0.25W of static power for 200K logic elements (LEs). The Cyclone III LS FPGAs, which are shipping now, target power and board-space-sensitive applications in all market segments including military and industrial.

The security features of the Cyclone III LS FPGA include a comprehensive information-assurance design suite that offers anti-tamper, design-security and design-separation capabilities.

To protect highly sensitive information, the Cyclone III LS FPGAs' anti-tamper features include JTAG port protection, tamper monitoring, and cyclical redundancy check (CRC). Offering another layer of protection, these devices feature a proven industry-standard AES 256-bit encryption key for design security.

Where size, weight, and power (SWaP) requirements are crucial, the design-separation feature of the Cyclone III LS FPGA enables high-assurance and industrial-safety applications in a single chip through logic, routing and I/O bank separation.

"The secret to the Cyclone series’ success has been a strong focus on customer applications, which allows Altera to supply the right mix of low power, high functionality, and small form-factor solutions," said Luanne Schirrmeister, senior director of component product marketing at Altera.

"The introduction of the Cyclone III LS devices extends Altera’s low-power leadership and specifically addresses the security needs that are paramount for the military and industrial markets. We're offering a complete solution that protects against IP theft and tampering."

Cyclone III LS FPGAs allow a single-chip solution for next-generation military applications such as software-defined radio (SDR), crypto-subsystems, and crypto modernization equipment where long battery life, density at the lowest power, and small board space are required.

The additional security features of the Cyclone III LS FPGAs give designers of secure communications applications the assurance that their information will be protected with anti-tamper technology.

Unique features of the Cyclone III LS FPGA also provide the optimal solution for industrial applications, specifically motion control, Industrial Ethernet, and industrial safety. Using the design-separation feature lowers system power and increases integration while offering design redundancy for safety-critical applications.

Cyclone III LS devices are shipping now. All of the devices will be supported in the Quartus II software version 9.0 SP2.

Aquantia deploys Synopsys IC Validator and IC Compiler for 40nm quad 10GBASE-T design

MOUNTAIN VIEW, USA: Synopsys Inc. today announced that Aquantia, an innovator in 10GBASE-T networking, has deployed Synopsys' recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, into production use at 40nm.

IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.

Compared to the typical implement-then-verify flow, the In-Design flow is instrumental in avoiding late-stage surprises and enabling integrated circuit (IC) providers like Aquantia - which is in the process of delivering an advanced 40nm-based quad 10GBASE-T solution - to achieve a faster, robust hand-off to the foundry.

"A few weeks can mean the difference between meeting or missing the market window in our fast moving market," said Ramin Shirani, vice president of engineering at Aquantia.

"IC Validator's ability to perform In-Design physical verification within IC Compiler reduces the physical verification effort from weeks to days by automating and accelerating one of the most onerous parts of our design cycle. We were impressed by IC Validator's fast convergence in concurrently implementing signoff metal-fill and DRC while reducing the timing impact of such implementation."

Prevailing physical verification flows are predominantly post-processing oriented, relying on modifications to the design after GDSII has been generated. These flows can lead to suboptimal results and can induce multiple discover-then-fix iterations.

Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue. Physical designers stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This time-intensive discover-then-fix loop is typically repeated on each block until the post-fill design is both signoff qualified and timing clean.

With In-Design physical verification, IC Validator and IC Compiler address the manufacturability issues within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.

While In-Design physical verification is enabled through tight integration with place and route, it is founded on a high-performance, foundry-endorsed, signoff-accurate engine in IC Validator. With a native multicore architecture, IC Validator can significantly accelerate the metal-fill process by up to 20 times.

For incremental fixes to metal fill near critical nets or ECOs, the In-Design flow enables rule-based, layer-based and area-based metal fill removal and re-insertion, thereby helping eliminate the need for costly full-chip runs.

"In-Design physical verification with IC Validator and IC Compiler is successfully addressing the increasing design-for-manufacturability needs of our customer base," said Saleem Haider, senior director of marketing, physical design and DFM at Synopsys.

"For meeting foundry-dictated manufacturing needs, Aquantia's adoption of IC Validator demonstrates the value of placing the emphasis on the 'D'in DFM and handling manufacturability requirements during design instead of post-design modifications."

TI intros low-cost Piccolo MCU motor control kits with PFC

BANGALORE, INDIA: Power factor correction (PFC) is becoming a key requirement for motor control applications, as regulation standards aimed to prevent spikes in the power grid are increasingly implemented.

Texas Instruments Inc. (TI) has announced two new Piccolo Motor Control Kits that enable PFC and sensorless field-oriented control of up to two motors with a single low-cost microcontroller (MCU).

Leveraging TI’s Piccolo MCUs and high-performance analog, the kits include everything needed to immediately begin development of cost-sensitive motor control applications such as pumps, HVAC, refrigerators and other appliances/white goods.

Allowing developers to efficiently meet their design needs, these controlCARD-based kits include a Piccolo controlCARD, Code Composer Studio IDE, software libraries and a hardware designer’s package. The Motor Control and PFC Developer’s Kit includes a single permanent magnet motor while the Dual Motor Control and PFC Developer’s Kit includes two.

Key features of Piccolo MCU Motor Control and PFC Developer’s Kits
* Single 60MHz TMS320F28035 MCU features 128KB flash and control-oriented peripherals such as 12-bit, 16 channel on chip ADC and high resolution PWM outputs.
* Sensorless field-oriented software tuned for kits’ motors allows developers to easily begin design right out of the box.
* Software is broken into incremental builds for easy, step by step learning and development of motor control plus PFC on Piccolo MCUs.
* Dual full bridge PWM motor drivers include programmable cycle-by-cycle current limit and two stage thermal protection capabilities.
* Isolated onboard USB JTAG emulation saves on cost by eliminating the need for an external JTAG emulator.
* Detailed documentation of field-oriented motor control theory and PFC principles, including instructions for executing both with one Piccolo MCU.

Altera Cyclone III LS -- first low power FPGAs with anti-tamper, design security, design separation

Altera has developed the industry's first low power FPGAs with anti-tamper, design security, and design separation. Extending low-power leadership, these low power FPGAs offer double the resources for less than 0.25W!

The image highlights how Altera is striving to extend its low power leadership with the Cyclone III LS devices.Source: Altera.

The Cyclone III LS devices offer up to 200K LEs for less than 0.25W of static power. It is said to be targeting power- and board-space-sensitive applications in all market segments. "Any market that requires low power and security features will require this product," said Ms Susan Chang, AP marketing manager for Cyclone Series, Altera, underlining the growing importance of low-power FPGAs into power-constrained applications. The devices are shipping to customers now.

A closer look at the Cyclone III LS FPGAs reveals the following:

Low power: 200K LE (logic elements) for under 0.25W; TSMC 60nm low-power (LP) process; and Quartus II software power-aware design flow.

* Information assurance design suite: Offering data protection for information-assurance applications, features include anti-tamper, design security, design separation and IP, design examples, etc.

* High functionality: Featuring densities ranging from 70K to 200K LEs; up to 8.2 Mbits of embedded memory; and up to 396 embedded multipliers.

The Cyclone III LS FPGAs are said to have the most comprehensive IP protection in an FPGA. It protects the IP with anti-tamper and design security. "There is a JTAG port protection to prevent reverse engineering," Chang added.

Security features include CRC to monitor for configuration changes, zeroizing the device if tampering is detected, and an on-chip oscillator that acts as an uninterruptible clock source for system monitoring.

Design separation features include single-chip redundancy and supporting information-assurance applications. This leads to reduction in power and board space, as well as reduction in BOM (bill of materials) cost -- by about 50 percent.

Yet another feature is that of data assurance with design separation. Designers can now create physically isolated partitions with design separation. This protects against time-dependent faults and SEU, and increases the system uptime as well. These enable achieving a higher level of integration on a single device.

Military market and SDR
According to Chang, the military market will be among the most important ones for these devices. Hence, Altera's clear thrust on design security and prevention of reverse engineering!

Focusing on the size, weight, and power (SWaP), these will support next-generation SDR waveforms with small footprint and low power (e.g., MUOS, SRW), night-vision goggles, and secure communications. It features crypto-modernization moving toward standardization.

The Cyclone III LS devices also support existing SDR (software-defined radio) applications. Chang said that SDR is one common design trend in the military market.

The next-generation software-defined radio (SDR) waveforms require more memory and logic for networking in the field and low power for extended battery life. Some other key requirements include small footprint for board space, data security for multiple channels in a single chip, and IP security and anti-tamper.

As far as the next-generation SDRs are concerned, these devices will facilitate reduction of the overall board space by up to 50 percent, an increase in the battery life by up to 2X, besides facilitating a single-chip secure SDR solution.

ST innovates integrated protection ICs for sleeker PoE equipment

SINGAPORE: Power over Ethernet (PoE), or IEEE 802.3at, is the industry standard enabling devices such as Voice-over-IP (VoIP) phones, wireless-LAN access points, RFID tag readers, sensors, or cameras to connect into a network without also requiring a nearby wall outlet for power.

This enhances convenience and flexibility for end users, and also reduces equipment costs, as no external AC/DC power adapter is required. In 2008, VDC Research Group predicted that annual shipments of PoE-enabled Ethernet switches will increase to over 132 million ports by 2012.

STMicroelectronics has simplified the design of equipment for powering devices connected to an Ethernet network by introducing an integrated surge-protection IC that meets Power-over-Ethernet specifications and protects against high-voltage surges, including electrostatic discharge (ESD).

ST’s PEP01-5841 protection IC is used in Power Sourcing Equipment (PSE), such as PoE-enabled Ethernet switches or hubs, which drive the specified 48V supply onto the Ethernet cable.

The PoE power-supply circuitry in the Ethernet hub or switch can withstand transients on the power lines of up to 100V. Extra protection is necessary to prevent very high voltage surges, such as ESD or EOS, from damaging the power supply.

Discrete components are usually used to clamp surges to a voltage below 121V (when specified), but the PEP01-5841 integrates a 100V clamping protection device and filtering capacitors for up to four PoE outputs in a single 5 x 6mm component. This simplifies design and saves up to 55 percent of pc-board printed-circuit-board space.

The PEP01-5841 is the first device providing 1kV surge protection as specified by IEC 61000-4-5 that also has a clamping voltage compatible with the 100V PSE controller. ESD protection satisfies worldwide standards including IEC 61000-4-2 and MIL-STD-883 Method 3015.

The PEP01-5841 is available immediately, in the industry-standard SO-8 package, priced at $0.25 in quantities of 10,000 pieces.

DSO highlights Dubai’s dynamic business environment during Japan visit

DUBAI, UAE: The Dubai Silicon Oasis Authority (DSOA), the regulatory body for the region’s leading high-technology park, today announced a high-ranking delegation held a five-day visit to Japan to meet with top officials and highlight the business potential of Dubai, particularly the investor-friendly environment of Dubai Silicon Oasis.

Led by Dr. Mohammed Al Zarouni, Chief Executive Officer of Dubai Silicon Oasis Authority, the delegation officials met with the Tsunehiro Ogawa, Director General-International Trade Policy from the Ministry of External Trade and Industry (METI), and the Yasuhiro Yamada, Executive Vice-President of Japan External Trade Organization (JETRO), as well as CEOs of leading Japanese corporations operating in the field of Semiconductor and Microelectronics industry. Discussions focused on the possibility of establishing business ties as well as exchanging views on a wide range of issues of mutual interest.Dr. Mohammed Al Zarouni with H.E Tsunehiro Ogawa-Director General, International Trade Policy from the Ministry of External Trade & Industry (METI).

Commenting on this visit, Dr. Al Zarouni said: "Dubai is already seen as a gateway to the Middle East and North Africa region. This is why we are keen to engage major Japanese firms in a dialogue that will lead to partnerships with DSO. Our talks specifically highlighted the advantages that DSO offers as a destination for Japanese firms to set up their regional base.

“The UAE is already one of the most IT enabled societies with a high degree of technology adaptation in the region. We believe the visit will further consolidate the existing synergy between technology companies in Japan and DSO and take our business ties to the next growth phase.”

Dr. Al Zarouni and the delegation also met with CEOs of leading Japanese corporations operating in the field of advanced technology, and briefed them on the investment opportunities that DSO offers.

The state-of-the-art infrastructure and facilities in Dubai in general and DSO in particular, which are specifically tailored to host technology companies, were also highlighted. The DSOA delegation additionally held discussions with senior officials of reputed banks and financial institutions that could support companies seeking to operate out of DSO.

The delegation later called on His Excellency Saeed Ali Al-Nowais, the UAE Ambassador in Japan. The diplomat expressed his willingness to facilitate all communication channels between the UAE and the Japanese companies planning to commence their operations in DSO and promote the investment opportunities in DSO especially for companies operating in the Semiconductor and Microelectronics industry. Dr. Al Zarouni also commended the role the UAE Ambassador is playing in strengthening the
bilateral trade between both countries.

DSO is a free zone technology park for semiconductors, microelectronics and other high technology-based companies looking to set up their regional headquarters and R&D facilities in the Middle East and North Africa region. DSOA is the regulatory body for DSO, the region’s premier integrated innovations hub for high-tech industries.