MOUNTAIN VIEW, USA: Synopsys Inc. today announced that the Common Platform technology alliance, a unique technology collaboration between IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, has qualified IC Validator for 32-nanometer (nm) process design rule checking on Common Platform technology.
Synopsys and the Common Platform companies are continuing with the collaboration to complete the qualification of IC Validator at 28nm on Common Platform technology. IC Validator, the newest addition to the Galaxy Implementation Platform, is a full signoff DRC/LVS solution.
In addition, the IC Validator has been uniquely architected as an ideal add-on to IC Compiler for in-design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
This qualification enables Common Platform customers to deploy IC Validator into production use at 32nm and see benefits from the productivity advantages of in-design physical verification in conjunction with the IC Compiler place and route solution.
"We believe that in-design physical verification is essential to significantly reduce physical verification turnaround time given the complexities at emerging nodes," said Henry Law, vice president, design services division for Chartered, on behalf of the Common Platform alliance companies.
"Architected for 45nm and below process nodes, IC Validator offers a highly flexible programming language that makes runset creation at these complex nodes easy and concise. Our qualification of IC Validator confirmed its signoff accuracy and productivity benefits of in-design physical verification. Given the observed benefits, we are committed to qualifying IC Validator for the Common Platform 28nm process node."
Prevalent approaches to physical design and verification can be described as "implement-then-verify" and result in multiple iterations between design and signoff. In-design physical verification accelerates design closure by enabling sign-off quality rule checking and fixing during the design process, avoiding late stage surprises that can jeopardize project schedules.
Other benefits include incremental processing, automatic error detection and fixing, near-linear scalability across multiple CPU cores and the elimination of expensive stream-outs and stream-ins. IC Validator also offers significant automation and innovative features such as DRC error classification or DRC waiver, multi-user collaboration, customized reporting and on-the-fly error reporting that can further improve physical verification turnaround time.
While in-design physical verification is facilitated by seamless integration with IC Compiler, IC Validator's foundry-endorsed, signoff-accurate engine is its core strength. Powered by its hybrid data and command-processing engine, IC Validator is a full signoff DRC/LVS tool offering the high accuracy necessary for leading-edge process nodes, excellent scalability for efficient utilization of available hardware and high programmability for easier runset development.
For runset writers and CAD managers, IC Validator offers a flexible programming language that can cut runset size from 2 to 10x, lowering the cost of setting up, maintaining and modifying the physical verification environment.
"Common Platform technology companies have always been at the forefront in defining high-productivity flows for advanced processes," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This qualification marks an important milestone in supporting leading-edge technology from the Common Platform alliance and will bring IC Validator's unique value proposition to our mutual customers and partners. We look forward to our continued collaboration towards the 28-nm qualification."
Showing posts with label IBM. Show all posts
Showing posts with label IBM. Show all posts
Wednesday, 30 September 2009
Monday, 17 August 2009
IBM scientists use DNA scaffolding to build tiny circuit boards
SAN JOSE, USA: Today, scientists at IBM Research and the California Institute of Technology announced a scientific advancement that could be a major breakthrough in enabling the semiconductor industry to pack more power and speed into tiny computer chips, while making them more energy efficient and less expensive to manufacture.
IBM Researchers and collaborator Paul W.K. Rothemund, of the California Institute of Technology, have made an advancement in combining lithographic patterning with self assembly -- a method to arrange DNA origami structures on surfaces compatible with today's semiconductor manufacturing equipment.
Today, the semiconductor industry is faced with the challenges of developing lithographic technology for feature sizes smaller than 22nm and exploring new classes of transistors that employ carbon nanotubes or silicon nanowires. IBM's approach of using DNA molecules as scaffolding -- where millions of carbon nanotubes could be deposited and self-assembled into precise patterns by sticking to the DNA molecules -- may provide a way to reach sub-22nm lithography.
The utility of this approach lies in the fact that the positioned DNA nanostructures can serve as scaffolds, or miniature circuit boards, for the precise assembly of components -- such as carbon nanotubes, nanowires and nanoparticles -- at dimensions significantly smaller than possible with conventional semiconductor fabrication techniques.
This opens up the possibility of creating functional devices that can be integrated into larger structures, as well as enabling studies of arrays of nanostructures with known coordinates.
"The cost involved in shrinking features to improve performance is a limiting factor in keeping pace with Moore's Law and a concern across the semiconductor industry," said Spike Narayan, manager, Science & Technology, IBM Research - Almaden. "The combination of this directed self-assembly with today's fabrication technology eventually could lead to substantial savings in the most expensive and challenging part of the chip-making process."
The techniques for preparing DNA origami, developed at Caltech, cause single DNA molecules to self assemble in solution via a reaction between a long single strand of viral DNA and a mixture of different short synthetic oligonucleotide strands.
These short segments act as staples -- effectively folding the viral DNA into the desired 2D shape through complementary base pair binding.
The short staples can be modified to provide attachment sites for nanoscale components at resolutions (separation between sites) as small as 6nm. In this way, DNA nanostructures such as squares, triangles and stars can be prepared with dimensions of 100-150nm on an edge and a thickness of the width of the DNA double helix.
The lithographic templates were fabricated at IBM using traditional semiconductor techniques, the same used to make the chips found in today's computers, to etch out patterns. Either electron beam or optical lithography were used to create arrays of binding sites of the proper size and shape to match those of individual origami structures.
Key to the process were the discovery of the template material and deposition conditions to afford high selectivity so that origami binds only to the patterns of "sticky patches" and nowhere else.
The paper on this work, "Placement and orientation of DNA nanostructures on lithographically patterned surfaces," by scientists at IBM Research and the California Institute of Technology will be published in the September issue of Nature Nanotechnology and is available at: http://www.nature.com/nnano/journal/vaop/ncurrent/abs/nnano.2009.220.html.
IBM Researchers and collaborator Paul W.K. Rothemund, of the California Institute of Technology, have made an advancement in combining lithographic patterning with self assembly -- a method to arrange DNA origami structures on surfaces compatible with today's semiconductor manufacturing equipment.
Today, the semiconductor industry is faced with the challenges of developing lithographic technology for feature sizes smaller than 22nm and exploring new classes of transistors that employ carbon nanotubes or silicon nanowires. IBM's approach of using DNA molecules as scaffolding -- where millions of carbon nanotubes could be deposited and self-assembled into precise patterns by sticking to the DNA molecules -- may provide a way to reach sub-22nm lithography.
The utility of this approach lies in the fact that the positioned DNA nanostructures can serve as scaffolds, or miniature circuit boards, for the precise assembly of components -- such as carbon nanotubes, nanowires and nanoparticles -- at dimensions significantly smaller than possible with conventional semiconductor fabrication techniques.
This opens up the possibility of creating functional devices that can be integrated into larger structures, as well as enabling studies of arrays of nanostructures with known coordinates.
"The cost involved in shrinking features to improve performance is a limiting factor in keeping pace with Moore's Law and a concern across the semiconductor industry," said Spike Narayan, manager, Science & Technology, IBM Research - Almaden. "The combination of this directed self-assembly with today's fabrication technology eventually could lead to substantial savings in the most expensive and challenging part of the chip-making process."
The techniques for preparing DNA origami, developed at Caltech, cause single DNA molecules to self assemble in solution via a reaction between a long single strand of viral DNA and a mixture of different short synthetic oligonucleotide strands.
These short segments act as staples -- effectively folding the viral DNA into the desired 2D shape through complementary base pair binding.
The short staples can be modified to provide attachment sites for nanoscale components at resolutions (separation between sites) as small as 6nm. In this way, DNA nanostructures such as squares, triangles and stars can be prepared with dimensions of 100-150nm on an edge and a thickness of the width of the DNA double helix.
The lithographic templates were fabricated at IBM using traditional semiconductor techniques, the same used to make the chips found in today's computers, to etch out patterns. Either electron beam or optical lithography were used to create arrays of binding sites of the proper size and shape to match those of individual origami structures.
Key to the process were the discovery of the template material and deposition conditions to afford high selectivity so that origami binds only to the patterns of "sticky patches" and nowhere else.
The paper on this work, "Placement and orientation of DNA nanostructures on lithographically patterned surfaces," by scientists at IBM Research and the California Institute of Technology will be published in the September issue of Nature Nanotechnology and is available at: http://www.nature.com/nnano/journal/vaop/ncurrent/abs/nnano.2009.220.html.
Monday, 27 July 2009
ARM, Chartered, IBM, Samsung and Synopsys to deliver vertically optimized solution for 32/28nm mobile SoC designs
SAN FRANCISCO, USA: In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor Manufacturing Ltd, IBM, Samsung Electronics Co. Ltd and Synopsys Inc. announced at the Design Automation Conference (DAC) an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices.
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
Tuesday, 14 July 2009
Soitec, IBM to develop wafer-level 3D integration technology
BERNIN, FRANCE: The Soitec Group (Euronext Paris), the world’s leading supplier of silicon-on-insulator (SOI) and other engineered substrates for the microelectronics industry, announced today that it has entered into collaboration with IBM to pioneer 22nm node and beyond silicon wafer substrate and bonding techniques that will enable wafer-level, three-dimensional (3D) integration technology for next-generation ICs.
The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM’s manufacturing roadmap.
The objective of this new collaboration is to develop highly flexible and cost-effective solutions for wafer-to-wafer stacking, a semiconductor technology designed to yield ICs with faster speeds and higher performance.
In joining IBM's 3D integration effort, Soitec will leverage its Smart Stacking technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).
"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, Vice President, Semiconductor Research and Development Center, IBM.
"Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”
“Soitec has continuously supported IBM’s development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program,” said Carlos Mazuré, CTO of Soitec.
The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM’s manufacturing roadmap.
The objective of this new collaboration is to develop highly flexible and cost-effective solutions for wafer-to-wafer stacking, a semiconductor technology designed to yield ICs with faster speeds and higher performance.
In joining IBM's 3D integration effort, Soitec will leverage its Smart Stacking technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).
"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, Vice President, Semiconductor Research and Development Center, IBM.
"Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”
“Soitec has continuously supported IBM’s development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program,” said Carlos Mazuré, CTO of Soitec.
Monday, 13 July 2009
MOSAID sues IBM for patent infringement
OTTAWA, CANADA: MOSAID Technologies Inc. announced that it has initiated litigation against IBM Corp. of Armonk, New York, for infringement of six of MOSAID's United States patents. The suit was filed today in the United States District Court for the District of Delaware.
In its complaint, MOSAID claims that IBM has infringed and is infringing MOSAID's patents by making and selling microprocessor and Application Specific Integrated Circuit (ASIC) products, which practice MOSAID's patents. MOSAID is claiming infringement of U.S. Patent Nos. 6,603,703; 6,580,654; 6,980,448; 7,038,937; 7,486,580; and 7,535,749. The patents were granted on MOSAID's fundamental Dynamic Random Access Memory (DRAM) circuit inventions.
"We are taking this action to protect our intellectual property because we have been unable to reach a reasonable settlement with IBM, despite many years of negotiation," said John Lindgren, President and CEO, MOSAID.
"We believe that IBM requires a license to our patents for its microprocessor and ASIC products that contain embedded DRAM. MOSAID has licensed virtually 100% of the global commodity DRAM industry, including signing patent license agreements covering embedded DRAM products. The value of our patents is internationally recognized."
MOSAID is represented by Howrey LLP, a top US law firm specializing in trademark and patent litigation.
In its complaint, MOSAID claims that IBM has infringed and is infringing MOSAID's patents by making and selling microprocessor and Application Specific Integrated Circuit (ASIC) products, which practice MOSAID's patents. MOSAID is claiming infringement of U.S. Patent Nos. 6,603,703; 6,580,654; 6,980,448; 7,038,937; 7,486,580; and 7,535,749. The patents were granted on MOSAID's fundamental Dynamic Random Access Memory (DRAM) circuit inventions.
"We are taking this action to protect our intellectual property because we have been unable to reach a reasonable settlement with IBM, despite many years of negotiation," said John Lindgren, President and CEO, MOSAID.
"We believe that IBM requires a license to our patents for its microprocessor and ASIC products that contain embedded DRAM. MOSAID has licensed virtually 100% of the global commodity DRAM industry, including signing patent license agreements covering embedded DRAM products. The value of our patents is internationally recognized."
MOSAID is represented by Howrey LLP, a top US law firm specializing in trademark and patent litigation.
Tuesday, 30 June 2009
IBM to provide application management services to Applied Materials
ARMONK, USA: IBM Corp. has signed a five-year strategic agreement to provide Applied Materials Inc., the global leader in nanomanufacturing technology solutions, with IT application development and maintenance services.
Under the agreement, IBM will be responsible for software application development, support and deployment. It will help centralize application support and increase efficiencies for Applied by providing a stable, flexible and scalable IT platform for its worldwide operations.
"As the leading provider of equipment to manufacture semiconductors, flat panel liquid crystal displays and solar photovoltaic cells, we depend on world-class operations within our enterprise," said Ron Kifer, Group Vice President and Chief Information Officer at Applied Materials.
"Information technology is a critical enabler of our business, and we selected IBM because it has the technical capabilities and portfolio of services to meet these needs worldwide."
IBM will provide Applied with an innovative service management framework that includes: application development, diagnostic and issue resolution support, database monitoring, security and controls monitoring, performance services, batch scheduling and data interface monitoring.
"In today's economy, our clients are looking for new ways to increase their IT efficiencies, and they are looking to service providers they can count on to help balance costs and system performance requirements," said Frank Kern, IBM Global Business Services. "With IBM's capabilities in application development and through its global delivery centers, we can help Applied Materials realize its business objectives."
Under the agreement, IBM will be responsible for software application development, support and deployment. It will help centralize application support and increase efficiencies for Applied by providing a stable, flexible and scalable IT platform for its worldwide operations.
"As the leading provider of equipment to manufacture semiconductors, flat panel liquid crystal displays and solar photovoltaic cells, we depend on world-class operations within our enterprise," said Ron Kifer, Group Vice President and Chief Information Officer at Applied Materials.
"Information technology is a critical enabler of our business, and we selected IBM because it has the technical capabilities and portfolio of services to meet these needs worldwide."
IBM will provide Applied with an innovative service management framework that includes: application development, diagnostic and issue resolution support, database monitoring, security and controls monitoring, performance services, batch scheduling and data interface monitoring.
"In today's economy, our clients are looking for new ways to increase their IT efficiencies, and they are looking to service providers they can count on to help balance costs and system performance requirements," said Frank Kern, IBM Global Business Services. "With IBM's capabilities in application development and through its global delivery centers, we can help Applied Materials realize its business objectives."
Wednesday, 24 June 2009
IBM charges up research into next-gen electric energy storage
SAN FRANCISCO, USA: IBM will gather many of the top minds in science, industry and technology to explore the next frontier of electrical energy storage and advanced battery systems -- key technologies that will power smarter energy grids, support widespread use of electric cars, and more -- at its annual Almaden Institute in San Jose, California, on August 26 and 27.
The goal of the 2009 Almaden Institute is to catalyze long-term, concerted efforts to create next-generation rechargeable batteries capable of storing 10 times more energy than today's most powerful Lithium-ion batteries. Speakers include Nobel Laureate and energy expert Burton Richter; Marc Tarpenning, co-founder of Tesla Motors; and Deborah Gordon, co-author of 2 Billion Cars.
"High density, scalable energy storage technologies are emerging as the greatest game changer for this new era of renewable energy sources and smarter grids," said Sharon Nunes, vice president, Big Green Innovations, IBM. "Today, the vast majority of the world's oil is burned for transportation. Energy sources, such as wind and solar power, fluctuate continuously. We believe the solution may lie in the development of an efficient, affordable energy storage network."
IBM Research's Almaden Institute brings together eminent, innovative thinkers from academia, government, industry, research labs and the media for an intellectually charged and vigorous dialogue that addresses fundamental challenges at the very edge of science and technology. Previous Almaden Institutes have launched major research projects in cognitive computing, service science and healthcare informatics.
Leveraging expertise in materials science, nanotechnology, green chemistry and supercomputing, scientists at IBM Research's Almaden lab in San Jose, California, are undertaking a multi-year research initiative around a grid-scale, efficient, affordable electrical energy storage network.
The team plans to explore rechargeable Lithium/Air systems, which have the greatest energy density of all practical battery systems and are inherently safer than traditional Lithium/ion systems.
IBM intends to partner with industry leaders, academia and others in this collaborative endeavor. The company would license any intellectual property that may result from this research rather than manufacturing battery cells.
IBM Research teams across the world apply advanced materials science, physics, modeling tools, materials science, physics, and integration expertise to address emerging environmental management opportunities.
IBM is focused on several areas related to energy and the environment, including energy efficient technology and services, carbon management, advanced water management, intelligent utility networks and intelligent transportation systems.
The company's focus on exploring battery technologies stems from IBM's Big Green Innovations initiative. Announced in November 2006, as part of IBM's investment in 10 new businesses generated by InnovationJam, Big Green Innovations has concentrated its efforts on water management, alternative energy and carbon management.
With decades of leadership in environmental stewardship, proven ability to solve complex challenges and unparalleled global reach, IBM is uniquely positioned to increase the efficiency of today's systems and enable our clients' "green" strategies.
The goal of the 2009 Almaden Institute is to catalyze long-term, concerted efforts to create next-generation rechargeable batteries capable of storing 10 times more energy than today's most powerful Lithium-ion batteries. Speakers include Nobel Laureate and energy expert Burton Richter; Marc Tarpenning, co-founder of Tesla Motors; and Deborah Gordon, co-author of 2 Billion Cars.
"High density, scalable energy storage technologies are emerging as the greatest game changer for this new era of renewable energy sources and smarter grids," said Sharon Nunes, vice president, Big Green Innovations, IBM. "Today, the vast majority of the world's oil is burned for transportation. Energy sources, such as wind and solar power, fluctuate continuously. We believe the solution may lie in the development of an efficient, affordable energy storage network."
IBM Research's Almaden Institute brings together eminent, innovative thinkers from academia, government, industry, research labs and the media for an intellectually charged and vigorous dialogue that addresses fundamental challenges at the very edge of science and technology. Previous Almaden Institutes have launched major research projects in cognitive computing, service science and healthcare informatics.
Leveraging expertise in materials science, nanotechnology, green chemistry and supercomputing, scientists at IBM Research's Almaden lab in San Jose, California, are undertaking a multi-year research initiative around a grid-scale, efficient, affordable electrical energy storage network.
The team plans to explore rechargeable Lithium/Air systems, which have the greatest energy density of all practical battery systems and are inherently safer than traditional Lithium/ion systems.
IBM intends to partner with industry leaders, academia and others in this collaborative endeavor. The company would license any intellectual property that may result from this research rather than manufacturing battery cells.
IBM Research teams across the world apply advanced materials science, physics, modeling tools, materials science, physics, and integration expertise to address emerging environmental management opportunities.
IBM is focused on several areas related to energy and the environment, including energy efficient technology and services, carbon management, advanced water management, intelligent utility networks and intelligent transportation systems.
The company's focus on exploring battery technologies stems from IBM's Big Green Innovations initiative. Announced in November 2006, as part of IBM's investment in 10 new businesses generated by InnovationJam, Big Green Innovations has concentrated its efforts on water management, alternative energy and carbon management.
With decades of leadership in environmental stewardship, proven ability to solve complex challenges and unparalleled global reach, IBM is uniquely positioned to increase the efficiency of today's systems and enable our clients' "green" strategies.
Friday, 24 October 2008
IDF Taiwan: Desktops with Intel Core i7; IBM, Intel ally on Blade servers
There's more news from IDF, Taiwan, folks! One, Intel is all set to launch high-end desktops powered by the Intel Core i7 processor, next month. This was disclosed by Kirk B. Skaugen, Vice President, Digital Enterprise Group, General Manager, Server Platforms Group, in the Digital Enterprise Keynote: IA = Embedded + Dynamic, during the recently held Intel Developer Forum (IDF).
Intel vPro technology-based business clients: "Piketown" for desktops and "Calpella" for notebooks, will be powered by future Nehalem processors and will provide corporate customers with even more enterprise-focused innovations.
Also, Intel and IBM strengthened their Blade server segment partnership. More of that a bit later!
According to Skaugen, we are in the third stage of the Internet revolution. "The fourth stage is the pervasive Internet. By 2015, there will be 15 billion devices connected to the Internet. The Atom processor has unleashed a new wave of connected devices. However, these devices will need massive infrastructure support as well. Storage will also become a massive area of growth and development," he added.
IBM Switch specs opened to SSI
According to Skaugen, the best infrastructure is built on infrastructure standards. Citing IDC figures, he said that the Blade market growth will be 37 percent CAGR during 2007-11. The Apac market will grow 78 percent.
IBM and Intel also strengthened their alliance in Blade servers. Mark Wiltse, IBM Systems & Technology Group, said that Blade.org has been created and is focused on solutions collaboration. "We are opening up the IBM Switch specifications to Server Systems Infrastructure (SSI). This will create broader opportunities in Blade. There is broad support for SSI Blade specifications." IBM will extend the BladeCenter switch specification for blade servers to the SSI on a royalty-free basis.
Commenting on the Nehalem, Skaugen added that it is a next generation microarchitecture, using second generation of virtualization, and there is 3X memory bandwidth support as well. Intel's Power Boost technology has also been used on the Nehalem.
Skaugen also provided details of next-generation high-end desktops powered by the Intel Core i7 processor, launching next month. These high-end desktops will provide outstanding performance for gaming and content creation applications.
Calpella and Piketown in the offing
He shared that the 2009 Intel vPro technology-based business clients codenamed "Piketown" for desktops and "Calpella" for notebooks will be powered by future Nehalem processors and will provide corporate customers with even more enterprise-focused innovations.
The upcoming Nehalem microarchitecture spans a range of products. First segments will include the Intel Core i7 processor and a variant designed for the efficient performance server segments codenamed "Nehalem-EP."
A derivative designed for the expandable server market segment ("Nehalem-EX") as well as other desktop and mobile versions ("Havendale," "Lynnfield," "Auburndale" and "Clarksfield") will be in production beginning in the second half of 2009.
Nehalem's integrated power gate
Stephen S. Pawlowski, Intel Senior Fellow, highlighted that the Nehalem has an integrated power gate. "We have got the M9 (metal 9) deposited on the silicon to create low-power resistance." Having power gates means that the idle cores use near zero power.
Several Intel partners also showcased their products at IDF Taiwan. There were 37 new motherboards, while the Nehalem EP was touted as the world's most adaptable server platform. Skaugen said: "it is energy efficient and designed for virtualization. Also, there is investment protection with FlexMigration."
32/64GB SSDs on offer
Intel also introduced its range of SSDs, in 2.5-inch form factors, with 32/64GB storage at the IDF.
Citing SSD benefits, he said these included 6X performance increase, 46X power reduction and 75 percent space reduction.
Intel vPro technology-based business clients: "Piketown" for desktops and "Calpella" for notebooks, will be powered by future Nehalem processors and will provide corporate customers with even more enterprise-focused innovations. Also, Intel and IBM strengthened their Blade server segment partnership. More of that a bit later!
According to Skaugen, we are in the third stage of the Internet revolution. "The fourth stage is the pervasive Internet. By 2015, there will be 15 billion devices connected to the Internet. The Atom processor has unleashed a new wave of connected devices. However, these devices will need massive infrastructure support as well. Storage will also become a massive area of growth and development," he added.
IBM Switch specs opened to SSI
According to Skaugen, the best infrastructure is built on infrastructure standards. Citing IDC figures, he said that the Blade market growth will be 37 percent CAGR during 2007-11. The Apac market will grow 78 percent.
IBM and Intel also strengthened their alliance in Blade servers. Mark Wiltse, IBM Systems & Technology Group, said that Blade.org has been created and is focused on solutions collaboration. "We are opening up the IBM Switch specifications to Server Systems Infrastructure (SSI). This will create broader opportunities in Blade. There is broad support for SSI Blade specifications." IBM will extend the BladeCenter switch specification for blade servers to the SSI on a royalty-free basis.
Commenting on the Nehalem, Skaugen added that it is a next generation microarchitecture, using second generation of virtualization, and there is 3X memory bandwidth support as well. Intel's Power Boost technology has also been used on the Nehalem.
Skaugen also provided details of next-generation high-end desktops powered by the Intel Core i7 processor, launching next month. These high-end desktops will provide outstanding performance for gaming and content creation applications.
Calpella and Piketown in the offing
He shared that the 2009 Intel vPro technology-based business clients codenamed "Piketown" for desktops and "Calpella" for notebooks will be powered by future Nehalem processors and will provide corporate customers with even more enterprise-focused innovations.
The upcoming Nehalem microarchitecture spans a range of products. First segments will include the Intel Core i7 processor and a variant designed for the efficient performance server segments codenamed "Nehalem-EP."
A derivative designed for the expandable server market segment ("Nehalem-EX") as well as other desktop and mobile versions ("Havendale," "Lynnfield," "Auburndale" and "Clarksfield") will be in production beginning in the second half of 2009.
Nehalem's integrated power gate
Stephen S. Pawlowski, Intel Senior Fellow, highlighted that the Nehalem has an integrated power gate. "We have got the M9 (metal 9) deposited on the silicon to create low-power resistance." Having power gates means that the idle cores use near zero power.
Several Intel partners also showcased their products at IDF Taiwan. There were 37 new motherboards, while the Nehalem EP was touted as the world's most adaptable server platform. Skaugen said: "it is energy efficient and designed for virtualization. Also, there is investment protection with FlexMigration."
32/64GB SSDs on offer
Intel also introduced its range of SSDs, in 2.5-inch form factors, with 32/64GB storage at the IDF.
Citing SSD benefits, he said these included 6X performance increase, 46X power reduction and 75 percent space reduction.
Friday, 25 April 2008
Encouraging developments in 22nm!
Suddenly, but steadily, there seems to be lot of work going on in the 22nm space. This can only be encouraging for the global semiconductor industry.
Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.
According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.
The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon "fin".
Early this month, Chartered Semiconductor Manufacturing, one of the world's top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.
IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.
And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.
PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.
Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.
He said: "The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower."
Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.
Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.
According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.
The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon "fin".
Early this month, Chartered Semiconductor Manufacturing, one of the world's top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.
IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.
And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.
PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.
Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.
He said: "The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower."
Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.
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