Magma's FineSim SPICE chosen by TLi as standard for verification of large analog IP designs

SAN JOSE, USA: Magma Design Automation Inc., a provider of chip design software, announced that Technology Leaders & Innovators (TLi), a global provider of consumer electronics products, has standardized on FineSim(tm) SPICE for verification of large analog IP designs.

TLi selected the Magma software after results of an exhaustive evaluation of a number of commercially available SPICE simulation products showed that FineSim SPICE, with its scalable multi-CPU capabilities, delivered runtime that was an order of magnitude faster than traditional multi-threaded simulators.

"We design many different types of analog circuits, including PLLs, ADC/DACs and high speed I/Os, that require extremely precise simulation during the design phase," said Soon-Won Hong, vice president at TLi.

"Through our evaluation, we found that FineSim SPICE provides 10 times faster simulation on a single CPU than other solutions, while meeting our accuracy requirements. Even more impressive was the scalable multi-CPU capability: we achieved better than 10 times faster simulation than conventional multi-threaded SPICE simulators. This dramatic speedup enables us to verify very large, post-layout, top-level netlists in SPICE, improving accuracy and allowing us to design and tape out with much more confidence in achieving first-pass silicon success."

"Enabled by Magma's Native Parallel Technology, FineSim SPICE offers significantly higher capacity and truly scalable multi-CPU performance while delivering silicon-accurate results," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "By ensuring first-time right silicon on large designs, FineSim SPICE helps customers like TLi reduce design and manufacturing costs and increase profit margins."

FineSim SPICE: Simulating advanced circuits
FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed-digital and analog designs. FineSim SPICE is a full SPICE simulation engine with distributed processing that enables customers to simulate large-scale mixed-signal system chips at the transistor level.

By providing increased speed and capacity while maintaining full SPICE accuracy, FineSim SPICE enables designers to simulate advanced circuits -- such as PLLs, ADCs, DACs and gigahertz SERDES (SERializers/DESerializers) -- that they previously would not even attempt using slower traditional SPICE simulators.

Calypto enables ESL design, verification of complex designs

Design Automation Conference 2009, SANTA CLARA, USA: Enabling electronic system level (ESL) design flows for increasingly complex system on a chip (SOC) devices, Calypto Design Systems Inc. announced the release of SLEC 4.0, the latest version of its popular sequential logic equivalence checking (SLEC) product family.

SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.

“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.

“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”

Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.

The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.

Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.

As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.

Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.

With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.

The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.

Mentor delivers hardware-assisted solution for accelerated verification of serial-ATA II products

WILSONVILLE, USA: Mentor Graphics Corp. has announced its hardware-assisted solution to accelerate the verification of Serial-ATA (SATA) II products, including hard disk drives (HDD) and optical CD/DVD drives.

This new solution enables designers to test their system-on-chips (SoCs) that control a HDD or optical drive by providing an accurate, hardware-based model of the real disk drive connected to their SoC.

This iSolve SATA product has a “plug-and-play” interface to the Veloce® family of hardware-assisted emulators, providing a cost-effective and efficient solution to verify SATA designs. The new product adds to the existing iSolve family of solutions for the accelerated verification of applications such as multimedia, networking, embedded systems, wireless, and storage devices.

The foundation stone of the consumer storage industry is based on the ATA (Advanced Technology Attachment) protocol, which has evolved into today’s widely used serial—ATA standard. With the ever-increasing demands from higher data transfer technologies, SATA has allowed manufacturers to push forward the operating speeds of storage devices to 3Gb/s with the application of the SATA II standard.

These devices play a major role in many of today’s products, from consumer to network storage devices, and place a heavy burden on SoC designers who need to verify how their designs interact with the SATA devices connected to them.

“New consumer and network storage products increasingly depend upon the use of the latest-generation SATA devices, and design engineers are concerned over how they can quickly and efficiently verify their SoC designs that connect to these devices,” said Jim Kenney, Mentor Emulation Division (MED) director of marketing.

“We took a new approach to solve these challenges with our iSolve SATA product by providing a flexible, easy-to-use, and highly configurable SATA device model. This gives our customers the ability to verify multiple configurations and descriptions of SATA devices, all with the same emulator solution rather than needing many specific devices.”

Combined with the Veloce emulation family, the iSolve SATA product delivers a high-performance and easy-to-use system verification environment to develop new SoCs containing a SATA controller without compromising delivery schedules. The solution offers several key benefits:

* Easy-to-use configuration tool means users are able to parameterize their SATA HDD or CD/DVD drive quickly and start their SoC verification as soon as possible.
* Productive debug environment provides access to low-level transactions to detect those hard-to-find bugs.
* High-speed data accesses to allow loading or unloading of GBytes of data in minutes rather than hours.
* Compliant to SATA 2.6 standard.

The iSolve SATA solution can be used with traditional in-circuit emulation (ICE) as well as a high-performance transaction-based acceleration mode of operation.

The ability to mix and match traditional ICE capabilities with high-performance, transaction-based acceleration facilitates the smooth transition from simulation-centric use models to in-circuit emulation. The solution is available for deployment at customer sites effective immediately.

ST-Ericsson adopts Synopsys MVSIM low power dynamic verification solution

Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform

MOUNTAIN VIEW, USA: Synopsys Inc. today announced that ST-Ericsson has adopted Synopsys' MVSIM low power dynamic verification solution for its STw8500 system-on-chip (SoC) platform for the mobile phone market.

ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs. The tool's extensive support for the IEEE 1801 [Unified Power Format (UPF)] power format, on which the STw8500 project team has standardized, was also a deciding factor.

"Mobile handset applications are driven by battery life, which necessitates the application of complex low power design techniques," said Francois Martin, director of the Wireless Multimedia Digital SoC's Business Unit at ST-Ericsson.

"We chose MVSIM because of its ability to comprehensively verify the advanced low power techniques we employ for our wireless designs and detect bugs early in our design cycle."

The voltage-level aware simulation in MVSIM enables accurate verification of low power designs and improves bug detection. Its comprehensive set of built-in, automated low power assertions boost verification productivity.

MVSIM, a core component of Synopsys' Eclypse Low Power Solution, is production-proven and works at the RTL and gate levels. MVSIM addresses complex low power verification challenges and enables customers to achieve their high-quality goals while meeting time-to-market constraints.

"The mobile phone market imposes some of the most stringent requirements on power and therefore demands the most advanced low power verification solution," said Swami Venkat senior director of functional verification marketing at Synopsys. "Synopsys continues to pioneer tools and methodologies to help address low power verification challenges, including the recent publication of the Verification Methodology Manual for Low Power (VMM-LP) book. ST-Ericsson's adoption of MVSIM confirms the tool's growing momentum in the mobile market segment."

eInfochips' DDR2 SDRAM SystemVerilog memory model generator tool

AHMEDABAD, INDIA: eInfochips, Inc. has announced the availability of a DDR2 SDRAM SystemVerilog Memory Model Generator. This HVL-based tool is an integrated solution to generate behavioral models for all leading memory vendors, such as Micron, Samsung, Hynix and Elpida, thereby shortening verification time and maximizing memory coverage.

“eInfochips strives to market solutions that add value to the design process,” states Sribash Dey, VP, North America Sales at eInfochips. “By offering high-quality simulation models and verification environments, we believe the DDR2 SDRAM memory model generator tool will reduce overall verification time and reduce development cost.”

With eInfochips’ DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.

Key features of memory generator tool
The DDR2 SDRAM memory generator is a TCL/TK-based tool that supports leading memory vendors and preserves a large library of part numbers for each supported memory vendor. The tool can be operated in two modes -- Typical Mode or Custom Mode. In the Typical Mode, a user may choose vendors and part numbers to generate the memory model. In the Custom Mode, a user may create a customized behavioral model from scratch by configuring the parameters of DDR2 SDRAM through the configuration selection algorithm (CSA).

Key features of generated behavioral models
The behavioral models are compliant to JEDEC standard JESD79 – 2D and ready to be plugged into a verification environment. The models offer built-in coverage and can be configured to turn on/off initialization, enable/disable DDR2 interface checkers and coverage.

Deliverables include verified SystemVerilog DDR2 SDRAM generator encrypted code, a user guide and release notes.

DDR2 SDRAM SystemVerilog memory generator tool is now available and comes with support.

Panasonic selects Magma’s FineSim SPICE for verification of large analog IP designs

BANGALORE, INDIA: Magma Design Automation Inc. announced that Panasonic Corp., one of the largest providers of consumer electronics products, standardized on Magma’s FineSim SPICE simulator with scalable multi-CPU technology for verification of large analog IP designs.

With FineSim SPICE in the production analog design flow, Panasonic designers have access to fast, accurate, high-capacity SPICE simulation technology that enables them to verify circuit performance of designs that previously were too large and complex to simulate. The ability to accurately predict performance of these large analog designs prior to manufacturing reduces the time and effort required for IC development and fabrication.

“Designing many different types of analog circuits requires very accurate SPICE simulations,” said Dr. Shiro Dosho, senior staff engineer of the Strategic Semiconductor Development Center of Panasonic. “Because of their extremely sensitive nature, verifying complex analog designs typically takes several weeks with SPICE simulators, if they can be simulated at all. With FineSim SPICE, we have seen effective speedup compared with a conventional SPICE simulator, while simulating much larger circuits never before practical in SPICE simulation – and we can verify our designs over multiple conditions.”

“Leveraging Magma’s Native Parallel TechnologyTM FineSim SPICE offers truly scalable multi-CPU performance and capacity while delivering silicon-accurate results,” said Anirudh Devgan, general manager of Magma’s Custom Design Business Unit. “This enables our customers to manufacture their ICs with confidence in meeting expected profit margins. We are pleased that Panasonic is standardizing on our technology for their most challenging consumer ICs.”

FineSim SPICE: Fast and accurate simulation
FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed digital and analog designs.

FineSim SPICE is a full SPICE simulation engine with distributed processing that enables customers to simulate large-scale mixed-signal system chips at the transistor level. By providing increased speed and capacity while maintaining full SPICE accuracy, FineSim SPICE enables designers to simulate advanced circuits -– such as PLLs, ADCs (analog-to-digital converters), DACs (digital-to-analog converters) and gigahertz SERDES (SERializer/DESerializer) -– that they previously would not even attempt using slower traditional SPICE simulators.

Synopsys on Discovery 2009, VCS2009 and CustomSIM

If you've been following the EDA industry closely, you'd be well aware of three major announcements by Synopsys over the last couple of days. These are:

* Synopsys introduced the Discovery 2009 verification platform, delivering faster, unified verification solutions.
* It unveiled the VCS multicore technology, delivering 2x verification speed-up.
* It introduced the CustomSim Unified Circuit Simulation solution, which addresses custom digital, analog and memory verification challenges.

I met up with Dr. Pradip K. Dutta, Corporate Vice President & Managing Director, Synopsys (India) Pvt Ltd and Manoj Gandhi, vice president and general manager, verification group @ Synopsys, in an attempt to understand how significant these announcements are for verification.

Verification is huge!
According to Manoj Gandhi, at the macro level, design complexities continue to grow. As this grows, one big challenge is verification. The reason is: today's SoC designs and large IC designs, they are being approached like large software projects.

He said: "Verification becomes huge, like software. It is expensive in hardware design. We focus on the verification challenges. We introduced the System Verilog about four to five years ago, and we had also acquired ArchPro. Yesterday, we announced the Discovery 2009, CustomSim and VCS2009."

How can users make use of new CPUs coming out? "We aim to get higher much performance using multicore architecture," he added.

Introducing VCS2009
The VCS2009 is multicore enabled, runs the industry's first low-power verification methodology, and enables fastest mixed-signal simulation with the CustomSIM. Focusing on the VCS2009, Gandhi said: "In verification, there's a design under test and verification. A lot of designs now have multicores. AMD is among the many folks using the VCS2009. Almost every CPU is designed using VCS. It plays a big role in large SoCs."

Design companies have several activities such as test bench, debug, etc. All of these can now be parallelized. "Customer designs can be simulated on multiple threads," Gandhi said. "Also, the applications can also be simulated on different threads, called application level parallelism. We can actually bring about 5-7X improvement in verification with the VCS2009."

According to him, this product is already being used by some large customers. "This is our next phase of performance innovation. The processor roadmap is getting more and more multicore. We have over 200 customers," he added.

The VCS distributes time consuming activities across multiple cores. Gandhi added that each core has a lot of computations. You may do lot of parallel activities with the mobile phones. All activities are now in parallel.

And how about the speed-up from parallel computation with the industry-leading Native Testbench (NTB)? He said: "We were one of the first to introduce all technologies as part of a single compiler. That brought the 5X speed-up. We did all of this in verification, and a test bench core was brought into verification."

The combination of DLP and ALP optimizes VCS performance over multicore CPUs. Design level parallelism (DLP) and application level parallelism (ALP) -- all CPUs can be threaded on different cores.

Low-power verification methodology published
Synopsys has published a book on industry's first low-power verification methodology, along with ARM and Renasas. It is an attempt to bring technology to the mainstream -- how to do low-power verification. There are other 30 companies who participated in this exercise.

On the CPF vs. UPF debate, he said that UPF is a standard where Magma, Mentor, Synopsys, etc. have participated. Cadence has CPF. Users can make use of this book and apply, on top of both UPF and CPF.

Introducing Discovery 2009
According to Synopsys, this solution is doing very well in the market. The company has seen strong technology leadership over the last two to three years. It has also created strong investments.

CustomSIM is a unified circuit simulation solution. "We have a software to silicon verification focus. We are all the way from system level design to RTL, to software verification, etc. Discovery has some technologies as part of that, noted Gandhi.

What has Synopsys done right?
A most interesting point in the EDA industry, I feel, has been the performance of Synopsys, in an otherwise difficult segment over the past year. So, what are the reasons behind this success?

Gandhi added: "Our management are all strong technologists. We have invested tremendously in bringing in strong technology leaders. In India, many companies needed R&D collaborations locally. For us, it was a big win when we invested in Bangalore. We work closely with customers delivering technologies that will address challenges two-three years from now.

Dr. Pradip Dutta elaborated: "Synopsys is very strong in product leadership (PL). The other two key areas are customer intimacy (CI) and operational excellence (OE). You need to be highest in PL. We have been very conservative even during strong times."

That is indeed a marvellous thought! Those who are typically strong in technology, generally go on to develop great intimacy with customers, and all of this starts reflecting on their operations, which are anyway excellent! Here's a message for those who wish to do well in tough times -- strong product leadership, coupled with customer intimacy and well, corresponding operational excellence!

Focus on verification
Now that the focus is quite clearly on verification, how do EVE and the other verification companies stand out? EVE is currently in the emulation space. Gandhi added that EVE competes more wtih Cadence and Mentor. "We work with EVE on many accounts. Verification is all about finding bugs. Emulation has been more cyclical."

According to him, Synopsys is now looking at tackling the next level -- how do you reduce the overall cost? "We will go beyond selling tools. We would look at how to identify issues and saving verification costs." I believe, verification takes up close to 70 percent of an overall design test.

Commenting on the EDA industry in India, both, Dr. Dutta and Gandhi feel it is still buzzing quite well, despite what's been happening in the global context. "We have invested quite a lot. We have a large team here. We continue to collaborate with local institutions here as well," Dr. Dutta added.

Despite EDA challenges, Mentor keeps faith on India

Great! All of these EDA firms, despite their current financial woes, remain strong and bullish on India! Mentor Graphics is no exception in this case!

It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.

Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.

We discussed a range of issues, such as the state of the EDA industry, Mentor's focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.

According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. "The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history," he says.

"We (the EDA industry) haven't had the growth rates we would like. However, we have done better. We have re-invented Mentor," adds Sawicki. "We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company." He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.

The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.

Flat growth likely for EDA
Commenting on EDA industry's growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: "EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software."

The other reason is that the aspects of manufacturing power and manageability will assume great importance. "Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability," he notes.

Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor's business has been from the automotive segment.

There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: "Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position."

So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.

On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. "You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power."

He advises that India has the ability to go beyond the innovation that has been happening.

Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.

Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. "We do not see any lull anywhere. Lot of design starts are happening here, in India," he adds.

I will continue my conversation with Joseph Sawicki in the next blog!

Cadence C-to-Silicon Compiler eliminates barriers to HLS adoption

Cadence Design Systems Inc. recently announced its C-to-Silicon Compiler, said to be the next-generation of HLS (high-level synthesis) technology.

The C-to-Silicon Compiler is said to eliminate historical barriers to HLS adoption to deliver the quality of results and net productivity gains engineers need. It also produces RTL (register transfer level) with quality at or above the 90th percentile of manual RTL design, while increasing the engineering productivity up to 10X. HLS incidentally, reduces the manual effort required to produce RTL, thereby enabling designers to avoid syntax errors common in traditional methodologies.

I was very fortunate enough to be able to speak directly with Steve Svoboda, marketing director for system level design products, Cadence, in the US, last evening, on the C-to-Silicon Compiler.

According to Svoboda, this tool can accurately predict timing estimates. Logic synthesis ability is embedded into the tool. Cadence logic sysnthesis has been embedded inside HLS. HLS transforms C and C++ into RTL.

What can this product actually do for the EDA industry? He says it can actually take EDA up to a new level in terms of delivering additional productivity to designers.

"When design compiler and logic synthesis came, it was during the golden era of the semiconductor industry. Productivity was increasing rapidly. But the problem is, since the early 1990s, there has been no real change in the RTL design methodology. The only productivity increase has come out in form of design re-use," he says.

"This (C-to-Silicon Compiler) could re-energize semiconductor and EDA industries by at least 10X times. About 20 years ago, there was 10X productivity increase. By having HLS, we can now close the gap and tackle the chips more effectively now."

So, first up, will C-to-Silicon Compiler compete with custom design projects? Svoboda it won't! Custom design projects typically utilize transistor-level design. C-to-Silicon is made to work within a standard ASIC design-flow.

Accelerate and improve verification
The C-to-Silicon Compiler will both accelerate and improve verification as well. The timing-approximate fast hardware models (FHMs) run 80-90 percent the speed of untimed C-models (or two-three orders of magnitude faster than RTL). This enables the hardware-software co-verification with greater timing accuracy.

The next question is: can people use third-party synthesis tools, along with the proprietary Cadence systhesis tool? Svoboda says that the C-to-Silicon Compiler outputs IEEE-standard Verilog RTL. Therefore, the output can go to any third-party synthesis tool. However, as the RTL output is generated using timing estimates from Cadence RTL Compiler, designers will get the best quality of results when using RTL Compiler for logic synthesis.

Will C-to-Silicon Compiler better predict performance and power? And if yes, has this cracked the low-power design issue? Svoboda adds that because of embedded logic synthesis, the C-to-Silicon Compiler can predict performance and (in principle) power better than other high-level synthesis tools.

He says: "Power estimation/optimization are key feature sets planned for upcoming releases of C-to-Silicon Compiler. We believe that those capabilities will enable the designers to create designs that are much better optimized for power, since design decisions with greatest power impact are made at the system-level."

Finally, how does C-to-Silicon compiler handle hardware allocation and scheduling operations? The answer is, C-to-Silicon Compiler handles hardware allocation and scheduling using various proprietary algorithms and heuristics. Many of these are based on previous research at Cadence Berkeley Labs.

Svoboda notes: "One should note that the better quality of results/performance of C-to-Silicon is due primarily to its inherent ability to generate more accurate timing-estimates than other HLS tools. The higher accuracy timing estimates result from the embedding of logic synthesis within the HLS tool/process, which enables gathering of full-context gate-level information to derive the timing estimates.

"Other HLS approaches rely on pre-characterization of technology libraries, which is not accurate enough, because those gate level estimates are only nominal values, and do not take into account the full-context of the design (fan-in, fan-out, buffers, etc.)"

Lastly, what happens to ESL (electronic system-level) tools? He believes that this tool will help the ESL market.

Svoboda says: "We now have a methodology to do design creation in C++ and SystemC. For example, they do virtual prototyping, hardware-software co-design, etc. In the past, when engineers created designs, they had to re-design in C++, etc. Our tool creates the RTL automatically for them. So, this could re-energize the ESL market very well."

It will be interesting to see what the other EDA firms such as Synopsys and Magma have in store!