Cadence intros first TLM-driven design and verification solution

SAN JOSE, USA: Cadence Design Systems Inc. recentlyintroduced the first unified TLM-driven design and verification solution and methodology enabling SoC designers to reap the benefits of transaction-level modeling (TLM).

The Cadence solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto sequential logic equivalence checking, the first version of the TLM-driven design and verification methodology, and customer adoption services.

The solution enables SoC TLM IP to be designed, synthesized and verified, resulting in faster design creation, increased functional verification productivity, and more opportunities to reuse design and verification IP.

“We have been employing high-level synthesis and TLM verification for several years, and verification methodology has proven to be quite challenging,” said Raimund Soenning, hardware development manager, Graphics Competence Center, Fujitsu Microelectronics GmbH.

“The Cadence methodology addresses the challenges we’ve experienced applying metric-driven verification from TLM through RTL, and mixing the two. We see significant opportunities to increase the reuse of our design and verification IP by following the comprehensive Cadence methodology.”

The new TLM-driven design and verification methodology encompasses SystemC modeling guidelines for virtual platforms and high-level synthesis, and defines the process for performing multi-language OVM-based functional verification of TLM, TLM/RTL, and RTL.

The methodology will be delivered in the form of manuals, self-paced tutorials, and workshops with hands-on labs. New solution capabilities include migration from C/C++ to enable automatic conversion of legacy design sources to SystemC TLM; high-level synthesis integrated with popular memory compilers to optimize for each architecture; and side-by-side analysis and traceability of SystemC and synthesized RTL.

The new TLM-driven methodology improves productivity, design quality, and project schedule predictability. Unlike prior technology, this comprehensive new solution enables customers to reuse TLM design and verification IP as golden source.

“Cadence is uniquely positioned to combine design and verification of TLM/RTL environments to address critical barriers to adoption,” said Michael McNamara, vice president and general manager, systems software group, Cadence Design Systems. “Focusing on the complete needs of the customer, we are delivering on the full promise of system-level design productivity.”

Calypto delivers ‘picture perfect’ ESL solution to Casio

SANTA CLARA, USA: Demonstrating the widespread adoption of its popular SLEC System HLS (High Level Synthesis) tool, Calypto Design Systems, a leader in sequential analysis technology, announced that Casio will incorporate SLEC into its electronic system level (ESL) design flow for new digital camera designs.

Casio plans to pair Calypto’s formal verification tool with the Cadence Design Systems' C-to-Silicon Compiler to improve design efficiency and reduce time-to-tomarket for its digital cameras.

The combination of the Cadence and Calypto technologies allows engineers to work at a much higher level of abstraction, engaging in true ESL design. Using C-to-Silicon Compiler, Casio will automatically generate synthesizable register transfer level (RTL) code from SystemC code that can then be comprehensively verified by SLEC SystemHLS.

The automated ESL flow will allow Casio to run multiple “what if” scenarios and evaluate different design implementations to ensure that the final product delivers the best combination of cost and performance possible while ensuring functional correctness.

“Digital camera design has become increasingly sophisticated, and gate complexity is now 10 times what it was just three years ago,” said Kazuyuki Kurosawa, section manager of Digital Camera Product Unit, Casio. “Before implementing an automated unified ESL flow, we were forced to engage in time-consuming RTL hand coding and verification through RTL simulation regressions to generate and verify our design –– a process that consumed valuable engineering resources and limited our ability to innovate. By automating these two complex steps, Calypto and Cadence allow us to reduce design time and focus our resources on bringing true differentiation to our products.”

“There is an ongoing effort for design teams to find ways to increase productivity and achieve faster time-to-market,” said Tom Sandoval, CEO Calypto Design Systems. “Cadence C-to-Silicon Compiler and its integration with Calypto’s SLEC SystemHLS are proven to meet this demand, allowing designers to use their valuable design time for innovation, rather than tedious simulation and coding.”

Cadence's C-to-Silicon Compiler bridges the gap between RTL design and system-level models, usually written in C/C++ and SystemC. Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.

By integrating their technologies, Cadence and Calypto deliver a fully automated system-level design solution that dramatically increases designer productivity.

“Our customers now have a best-in-class comprehensive solution for system level design and verification,” said Michael McNamara, vice president and general manager of the Systems Software Group at Cadence Design Systems. “The tight integration between Calypto’s SLEC SystemHLS and Cadence C-to-Silicon Compiler gives our customers an optimal flow that is rapidly becoming a standard approach for advanced SoC design.”

Cadence's focus -- systems, low power, enterprise verification, mixed signal and advanced nodes

I recently had the opportunity of meeting up with Nimish Modi, Senior Vice President, Research and Development, Front-End Group, Cadence Design Systems, along with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd.

Modi provided a perspective on how solutions from the EDA sector help the electronic design industry improve productivity, predictability and reliability of design processes, especially verification. Design verification is the process of ensuring that a chip design meets its specifications.

According to him, today's product development ecosystem comprises of three driving forces -- productivity, predictability and reliability. "We are clearly at the core of product development. We have a very strong breadth and depth. There is a layer of solutions we have integrated with our product offerings," he added.

He highlighted that Cadence's solutions consist of integrated point tools, as well as recommended use models. It also has a very strong services offering.

Focus on five key areas
Currently, Cadence is focusing on five key areas -- systems, low power, enterprise verification, mixed signal and advanced nodes. "We have a solutions oriented approach across the board," Modi said.

On systems, it is key to focus on gaining more productivity. Modi said: "This can be done by raising the level of abstraction. The technologies available to address ESL have been around for a while, each one addressing a piece of the puzzle. The need is there for seeing tremendous improvements in that. Here, Cadence's C-to-Silicon Compiler comes in."

"The other piece is -- it has incremental synthesis capabilities. A third thing -- it is connected to the downstream flow. This is the foundation of our systems strategy," said Modi.

Coming to the systems design and verification strategy, the first component involves planning and management. "We have an enterprise manager," he added. Cadence has been a leader in the hardware assisted verification with rich VIP/SpeedBridge portfolio. It has enabled a move to TLM driven design and verification flow. Cadence also delivers unique system power exploration, estimation and optimization flow. It provides unique hardware/software co-verification capabilities (Incisive Software eXtensions) as well.

Low power strategy
On Cadence's low power strategy, Modi highlighted three components -- implementation, verification and design. "The innovation was the ability to create a power format to capture the design intent. We are committed to providing flow operability as well. We want customers to make use of advanced power management techniques," he added.

"We have the superior low power technology," he claimed, referring to the Power Forward Initiative (PFI). "Look at technology -- that is proven. The format is a means to the end. We are also working on providing more capabilities in the power exploration space. We are working under different aspects.

"You can do power analysis on the IP block; there's C-to-Slicon, which has power as a function; multi-supply voltage will be a component of our synthesis solution. All of these vectors are driving the power exploration space. Seventy percent of chips' power is determined at or before the RTL stage," said Modi.

Cadence has a closed loop verification methodology. At each stage, you can go back and make sure you can be consistent with what's there upfront.

Enterprise verification strategy
On enterprise verification, Cadence's approach is plan-to-closure. Predictability -- utilize executable plans and metrics that predict functional closure; productivity -- effectively deploy methodolgy driven multispecialist flows. with VIP and multiproduct automation; and quality -- reduce risk of functional bugs at tape-out at various project stages.

Modi added: "Our verification IP portfolio is also very critical. The depth of our portfolio is the broadest in the industry. In verfication, the actual TAM is growing. We are getting opportunities as well. Multi dimensions of enterprise verification are being taken care of by us."

Interesting that all EDA companies have focused on verification! Why now and why not earlier? Modi said: "We've been in this area for a while. We have pioneered the new approaches. The goal is: how do you know it is good enough to hit the tapeout button? Our goal is to raise the confidence of customers."

He added: "We are coming uo with a hybrid model. We are engaging with customers at this point of time. We came up with multi-language support in OVM. We have 30+ verification IP portfolios."

Trends in complex SoCs
Today, it is largely a mixed signal world. Mixed signal IC revenue has been increasing faster than the rest of the industry. It is driven by applications, including wireless devices, consumer and DTV, and automotive.

Modi said: "There is a genuine need to support natively analog behavioral models in a digital centric verification environment. Mixed signal is a larger percentagre of area and effort."

Coming down to advanced nodes, it is no surprise that Cadence definitely supports MCMM (multicorner and multimode). "It is part of our Encounter Digital Implementation System," added Modi.

Cadence C-to-Silicon Compiler eliminates barriers to HLS adoption

Cadence Design Systems Inc. recently announced its C-to-Silicon Compiler, said to be the next-generation of HLS (high-level synthesis) technology.

The C-to-Silicon Compiler is said to eliminate historical barriers to HLS adoption to deliver the quality of results and net productivity gains engineers need. It also produces RTL (register transfer level) with quality at or above the 90th percentile of manual RTL design, while increasing the engineering productivity up to 10X. HLS incidentally, reduces the manual effort required to produce RTL, thereby enabling designers to avoid syntax errors common in traditional methodologies.

I was very fortunate enough to be able to speak directly with Steve Svoboda, marketing director for system level design products, Cadence, in the US, last evening, on the C-to-Silicon Compiler.

According to Svoboda, this tool can accurately predict timing estimates. Logic synthesis ability is embedded into the tool. Cadence logic sysnthesis has been embedded inside HLS. HLS transforms C and C++ into RTL.

What can this product actually do for the EDA industry? He says it can actually take EDA up to a new level in terms of delivering additional productivity to designers.

"When design compiler and logic synthesis came, it was during the golden era of the semiconductor industry. Productivity was increasing rapidly. But the problem is, since the early 1990s, there has been no real change in the RTL design methodology. The only productivity increase has come out in form of design re-use," he says.

"This (C-to-Silicon Compiler) could re-energize semiconductor and EDA industries by at least 10X times. About 20 years ago, there was 10X productivity increase. By having HLS, we can now close the gap and tackle the chips more effectively now."

So, first up, will C-to-Silicon Compiler compete with custom design projects? Svoboda it won't! Custom design projects typically utilize transistor-level design. C-to-Silicon is made to work within a standard ASIC design-flow.

Accelerate and improve verification
The C-to-Silicon Compiler will both accelerate and improve verification as well. The timing-approximate fast hardware models (FHMs) run 80-90 percent the speed of untimed C-models (or two-three orders of magnitude faster than RTL). This enables the hardware-software co-verification with greater timing accuracy.

The next question is: can people use third-party synthesis tools, along with the proprietary Cadence systhesis tool? Svoboda says that the C-to-Silicon Compiler outputs IEEE-standard Verilog RTL. Therefore, the output can go to any third-party synthesis tool. However, as the RTL output is generated using timing estimates from Cadence RTL Compiler, designers will get the best quality of results when using RTL Compiler for logic synthesis.

Will C-to-Silicon Compiler better predict performance and power? And if yes, has this cracked the low-power design issue? Svoboda adds that because of embedded logic synthesis, the C-to-Silicon Compiler can predict performance and (in principle) power better than other high-level synthesis tools.

He says: "Power estimation/optimization are key feature sets planned for upcoming releases of C-to-Silicon Compiler. We believe that those capabilities will enable the designers to create designs that are much better optimized for power, since design decisions with greatest power impact are made at the system-level."

Finally, how does C-to-Silicon compiler handle hardware allocation and scheduling operations? The answer is, C-to-Silicon Compiler handles hardware allocation and scheduling using various proprietary algorithms and heuristics. Many of these are based on previous research at Cadence Berkeley Labs.

Svoboda notes: "One should note that the better quality of results/performance of C-to-Silicon is due primarily to its inherent ability to generate more accurate timing-estimates than other HLS tools. The higher accuracy timing estimates result from the embedding of logic synthesis within the HLS tool/process, which enables gathering of full-context gate-level information to derive the timing estimates.

"Other HLS approaches rely on pre-characterization of technology libraries, which is not accurate enough, because those gate level estimates are only nominal values, and do not take into account the full-context of the design (fan-in, fan-out, buffers, etc.)"

Lastly, what happens to ESL (electronic system-level) tools? He believes that this tool will help the ESL market.

Svoboda says: "We now have a methodology to do design creation in C++ and SystemC. For example, they do virtual prototyping, hardware-software co-design, etc. In the past, when engineers created designs, they had to re-design in C++, etc. Our tool creates the RTL automatically for them. So, this could re-energize the ESL market very well."

It will be interesting to see what the other EDA firms such as Synopsys and Magma have in store!