Magma broadens support for TSMC processes

SAN JOSE, USA: Magma Design Automation Inc. announced that Quartz DRC and Quartz LVS rule decks are available for TSMC 180-nanometer (nm) process technologies. With this addition, designers can now download 40-nm, 65-nm, 90-nm, 130-nm and 180-nm rule decks for Quartz DRC and Quartz LVS from the TSMC-Online website.

"We have been working with Magma's Quartz DRC and Quartz LVS for advanced process nodes for several years, and have tested their accuracy using the same rigorous testing procedures we use for all DRC and LVS tools," said Tom Quan, deputy director of Design Service Marketing at TSMC. "In response to customer demand, we have now expanded support for Quartz DRC and Quartz LVS to include 180 nm."

Quartz DRC and Quartz LVS are architected to process integrated circuit (IC) designs of any size, at any technology node, in the least amount of time. Magma's is the first truly scalable physical verification solution, able to provide turnaround time that is up to an order of magnitude faster than existing solutions.

The Quartz tools are fully compatible with third-party IC implementation flows and can read file formats used by traditional physical verification tools.

"TSMC has been a key foundry partner with Magma, and our mutual customers have used Quartz physical verification solutions to tape out some of the largest, most aggressive designs in the world," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit.

"Many ICs are still being implemented in lower-cost 180-nm processes. Now that TSMC has made 180-nm rule decks available, more designers will be able to leverage the speed and accuracy of Quartz DRC and Quartz LVS."

Magma's Quartz deployed by NVIDIA as primary design rule checker for 40nm and below

SAN JOSE, USA: Magma Design Automation Inc., a provider of chip design software, announced that its Quartz DRC has been deployed by NVIDIA Corp. as the primary physical verification checker for designs targeted at 40-nanometer (nm) and smaller process nodes.

NVIDIA, which invented the graphics processing unit and continues to lead its development, is using the Magma physical verification tools for applications ranging from custom cell development to full-chip verification. NVIDIA selected Quartz for 40 nm and below after use on multiple 65-nm designs and finding they delivered significantly faster turnaround time than existing physical verification tools.

"We have been using Magma's Quartz physical verification solution in production since we moved to the 65-nm process node, and it has proven to be both accurate and significantly faster than other solutions," said James Chen, VLSI technology manager at NVIDIA. "Through dozens of tapeouts, we've seen that Quartz provides the sign-off accuracy needed via certified runsets provided by our foundry partners. Though design sizes and rule complexity have increased significantly, we've been able to meet aggressive design schedules by leveraging Quartz's linear scalability on standard, low-memory Linux machines."

Quartz DRC and LVS are architected to process integrated circuit (IC) designs of any size, at any technology node, in the least amount of time. Magma's is the first truly scalable physical verification solution, able to provide turnaround time that is up to an order of magnitude faster than existing solutions while using existing compute resources. The Quartz tools are fully compatible with third-party IC implementation flows and can read file formats used by traditional physical verification tools.

"Quartz DRC and LVS have enabled silicon success for a wide range of customers, including those doing the most advanced designs in the world," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "NVIDIA's decision to deploy Quartz as the primary physical verification design rule checker for 40-nm and smaller process nodes is an endorsement of the software's ability to provide the fastest turnaround-time while using very cost-effective hardware systems."

Magma customers pass 50-tapeout mark at 45/40nm using Talus

BANGALORE, INDIA: Magma Design Automation Inc. today announced Magma customers have passed the 50-tapeout mark for chips designed at 45 nanometer (nm) or smaller geometries using Magma’s Talus netlist-to-GDSII design implementation system –- more than with any other EDA supplier’s implementation system.

Talus, Magma’s next-generation implementation platform designed specifically for chips at 45-/40-nm or smaller process nodes, is now widely used among Magma customers and its latest release, Talus 1.1, has demonstrated particular advantages for designs at the 45-/40-nm process nodes.

More than 55 percent of the 45- and 40-nm tapeouts were completed for networking and mobile applications. Other applications taking advantage of 45- and 40-nm technology include multimedia and graphics.

In terms of geographic distribution, about 70 percent of the 45- and 40-nm tapeouts completed to date were by companies based in North America and about 25 percent by companies based in Japan or the Asia-Pacific region.

“As you might expect, networking and mobile applications represent the bulk of chips completed at 45 or 40 nm,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.

“The designs completed so far at these geometries tend to be complex, in some cases approaching 100 million gates. Talus 1.1 with its COre™ (concurrent optimizing routing engine) and high capacity is ideally suited for implementing chips in these application areas which tend to push the performance envelope as well as have high gate counts.”

Talus 1.1: Fastest path to silicon for 45-/40-nm chips
The Talus system was built to anticipate the unique requirements of chip design at advanced process nodes, and Talus 1.1 takes its capabilities even further. Since its availability was announced in May 2009, Magma customers have found Talus 1.1 to deliver significant improvements in runtime and timing convergence.

It also achieves timing closure with no design-rule checking (DRC) violations and reduces total chip area significantly. Talus also offers a significant capacity advantage over competing systems which allows design teams to work on much larger blocks during the design process.

“Magma’s raison d’etre from our beginning has been to provide designers with the best technology for advanced chips,” Buch added. “That’s why we closely track how many chips are taped out as the semiconductor community transitions to new process geometries.

“The transition to the 45-/40-nm nodes has again created an opportunity for Magma to expand market share. Of course, we are not stopping there and already have the foundation in place to support the next process node at 32/28nm. In fact, we are already seeing some of our customers working on 28-nm designs.”

Magma's FineSim SPICE chosen by TLi as standard for verification of large analog IP designs

SAN JOSE, USA: Magma Design Automation Inc., a provider of chip design software, announced that Technology Leaders & Innovators (TLi), a global provider of consumer electronics products, has standardized on FineSim(tm) SPICE for verification of large analog IP designs.

TLi selected the Magma software after results of an exhaustive evaluation of a number of commercially available SPICE simulation products showed that FineSim SPICE, with its scalable multi-CPU capabilities, delivered runtime that was an order of magnitude faster than traditional multi-threaded simulators.

"We design many different types of analog circuits, including PLLs, ADC/DACs and high speed I/Os, that require extremely precise simulation during the design phase," said Soon-Won Hong, vice president at TLi.

"Through our evaluation, we found that FineSim SPICE provides 10 times faster simulation on a single CPU than other solutions, while meeting our accuracy requirements. Even more impressive was the scalable multi-CPU capability: we achieved better than 10 times faster simulation than conventional multi-threaded SPICE simulators. This dramatic speedup enables us to verify very large, post-layout, top-level netlists in SPICE, improving accuracy and allowing us to design and tape out with much more confidence in achieving first-pass silicon success."

"Enabled by Magma's Native Parallel Technology, FineSim SPICE offers significantly higher capacity and truly scalable multi-CPU performance while delivering silicon-accurate results," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "By ensuring first-time right silicon on large designs, FineSim SPICE helps customers like TLi reduce design and manufacturing costs and increase profit margins."

FineSim SPICE: Simulating advanced circuits
FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed-digital and analog designs. FineSim SPICE is a full SPICE simulation engine with distributed processing that enables customers to simulate large-scale mixed-signal system chips at the transistor level.

By providing increased speed and capacity while maintaining full SPICE accuracy, FineSim SPICE enables designers to simulate advanced circuits -- such as PLLs, ADCs, DACs and gigahertz SERDES (SERializers/DESerializers) -- that they previously would not even attempt using slower traditional SPICE simulators.

Magma Quartz DRC and Quartz LVS support TSMC’s unified physical verification format

BANGALORE, INDIA: Magma Design Automation Inc. announced that Quartz DRC and Quartz LVS now support TSMC’s interoperable design rule check (iDRC) and layout-versus-schematic (iLVS).

With the two unified electronic design automation (EDA) data formats and scalable Quartz physical verification solution, Magma and TSMC are working to make their mutual customers’ adoption of TSMC’s 40nm process technology faster, easier and less costly.

"TSMC has taken a leadership role in defining an interoperable, common language for all DRC and LVS tools," said ST Juang, senior director of Design Infrastructure Marketing at TSMC.

“The unified iDRC and iLVS files eliminate the need to develop and maintain multiple custom runsets, improve data accuracy and consistency, and enables designers to choose the EDA tool that best meets their requirements. Ultimately, our customers can adopt our advanced process technologies early for their designs.”

Quartz DRC and Quartz LVS are architected to process integrated circuit (IC) designs of any size, at any technology node, in the least amount of time. Magma's is the first truly scalable physical verification solution, able to provide turnaround time that is up to an order of magnitude faster than existing solutions by leveraging existing compute resources.

The Quartz tools are fully compatible with third-party IC implementation flows and can read file formats used by traditional physical verification tools.

“The scalable architecture of Quartz DRC and Quartz LVS was designed specifically to provide fast, efficient physical verification of large, complex designs,” said Anirudh Devgan, general manager of Magma’s Custom Design Business Unit.

“That scalability and native support for the Tcl procedural language used by the TSMC iDRC and iLVS formats make Quartz DRC and Quartz LVS the ideal solution for designs targeting TSMC’s processes.”

Magma's next-gen mixed-signal design flow with new Titan release

SAN JOSE, USA: Magma Design Automation Inc. has announced a new release of the Titan(tm) mixed-signal design platform, which now includes the state-of-the art Titan Analog Simulation Environment (ASE) and Titan Schematic-Driven Layout (SDL) tools.

Several productivity enhancements have also been made to the existing Titan Schematic Editor (SE), Titan Layout Editor (LE) and Titan Shape-Based Router (SBR). With the new capabilities and enhancements, Titan delivers first-time-right, predictable mixed-signal designs, shortening the design process by weeks without sacrificing performance.

Titan is the first truly unified, open platform that embeds digital standard-cell design into the analog circuit design flow. Seamless integration with Magma's Talus digital implementation, Titan ADX accelerator, FineSim simulation and Quartz physical verification tools provides greater automation and reduces iterations during both block-level design and top-level integration.

To ease adoption, Titan natively supports OpenAccess and emerging industry standards such as the TSMC iPDK.

"Since we introduced Titan a little over a year ago we've diligently worked to deliver critical enhancements and to meet key milestones in the development of this unique platform," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit.

"Our efforts have paid off. Titan has been adopted by leading semiconductor companies, qualified by the world's largest foundry for an important new initiative and even nominated for innovation awards. With the addition of the recent enhancements and Titan ASE and Titan SDL, Magma's Titan is the fastest path to mixed-signal silicon."

Titan Platform
Titan is the first full-chip mixed-signal design, analysis and verification platform. Unlike other design solutions, Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation and verification, providing comprehensive capabilities.

Titan SE, a complete and powerful schematic editor, facilitates quick schematic capture and editing, advanced search and replace, easy hierarchy traversal and design management. It has full support for buses and bundles, inherited connections and netlisting of various formats.

Titan ASE, a specification-driven, test-based analog simulation environment, empowers organized design verification across different operating conditions. Pass-fail indicators locate the failing cases and indicate final signoff with respect to the specifications. Features such as simulator-independent tests, device under text (DUT)-based test mapping help migrate the test benches across different versions of the design.

Titan SE, Titan ASE and Titan ADX capabilities are integrated to enable easy capture of the design along with the user constraints and fast verification of the optimized design with FineSim. The template-based design and organized characterization framework ease verification of the implementation generated by Titan ADX.

Titan SDL enables the creation of a connectivity-aware layout using any language pcells. Cross-probing, flyline displays during move and wiring, check and update of design data and opens and shorts locator functions minimize the physical verification loop by ensuring a layout-vs.-schematic (LVS)-correct layout.

Pattern-based device module generation accelerates the analog layout placement. Titan SDL also allows one instance to be bound to many instances between the schematic and layout.

Titan LE provides a complete set of features to accomplish full-custom layout design in fewer clicks. Its high capacity and speed coupled with the embedded Talus digital implementation capabilities provides mixed-signal chip integration within a single environment. Titan LE also provides advanced features like live-DRC, automatic guard-ring creation, net tracing, pcell abutment and interactive wire creation that includes bus routing.

Titan SBR provides constraints such as shielding, differential pair routing, star and matched routing, enabling this shape-based router to achieve highly precise analog routing results. Titan SBR can run on both the Titan and Talus database.

The Titan platform is also integrated with the Quartz DRC and Quartz LVS physical verification tools. Design rule checking (DRC) can be performed on mixed-signal designs and also run in an incremental mode to speed DRC error fixing.

FineSim Pro works with Titan to enable full-chip SPICE-level simulation and post-layout simulation with extracted parasitics.

Magma's Titan mixed-signal design platform will be available in August 2009.

Magma's Talus included in TSMC Reference Flow 10.0

SAN JOSE, USA: Magma Design Automation Inc. announced that the Talus IC implementation system has been included in TSMC Reference Flow 10.0.

With Magma software and the latest TSMC Reference Flow, designers have access to the "Fastest Path to Silicon" for designs targeted at TSMC's 28nm processes.

"TSMC 28-nm processes offer the promise of billion-gate ICs, but also bring the challenge of dealing with more physical effects, tougher power requirements and difficult timing closure issues," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Magma's latest release, Talus 1.1 with our new COre(tm) technology, combined with TSMC's Reference Flow 10.0, provides faster design closure on large, tough designs."

COre is Magma's new Concurrent Optimizing routing engine. This new routing engine, which includes the ability to push critical wires to a thicker and wider metal layer, supports TSMC's 28-nm design rules and provides faster overall design closure with better performance and predictability.

"For years TSMC has been leveraging close collaboration with leading EDA vendors, such as Magma, to co-optimize EDA design technology and our advanced process technology," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

"With the inclusion of the Talus system for Reference Flow 10.0, TSMC and Magma offer mutual customers differentiated design and process technologies that improve power, performance and design for manufacturability of 28-nm ICs."

Enabling 28-nm design through Open Innovation Platform (OIP)
Through the OIP and Active Accuracy Assurance initiative, TSMC enables innovation by promoting quality and accuracy throughout the semiconductor ecosystem. Magma software has supported the OIP since the platform's inception.

Magma works closely with TSMC and mutual customers early in the process to ensure product enhancements satisfy customers' deployment requirements. By engaging with TSMC and customers early, Magma has ensured that Talus is able to implement designs targeted at TSMC's 28-nm processes.

Enhanced low-power design techniques
Low-power support in Reference Flow 10.0 has been expanded to include the bottom-up hierarchical Unified Power Format (UPF) flow. The UPF can be used to specify low-power design techniques at all levels of a hierarchical design flow.

For low-power flows with multiple voltage islands, support for disjoint power domains with dual power SRAMs is now available. To address leakage, Talus is able to optimize leakage at different corners from timing optimization. This provides more accurate timing and leakage optimization, minimizing iterations. Talus also supports the Common Power Format (CPF) as part of its low-power flow.

Ensuring manufacturability at 28nm
To address design for manufacturability (DFM) and variability issues at 28 nm, Magma integrates Talus qDRC physical verification capabilities into the Talus Vortex place-and-route flow. This solution provides highly accurate timing-driven metal fill that is design-rule clean and meets timing and performance requirements.

Other physical DFM capabilities include lithography hotspot fixing within Talus based on TSMC qualified lithography process check (LPC) hotspot detection engines. By fixing hotspots within the Talus unified design environment, area and timing penalties can be avoided and a design-rule-clean layout is generated.

For electrical DFM, TSMC provides an integrated eDFM (electrical DFM) analysis, which is a combination of DFM effects on chemical mechanical polishing (CMP), Thickness-to-Electrical (T2E), lithographic Shape-to-Electrical (S2E), and stress effects.

Talus provides complete support for TSMC's eDFM-based timing analysis and optimization.

Toshiba deploys Magma Talus for 90-, 65- and 40-nm ASICs and ASSPs

BANGALORE, INDIA: Magma Design Automation Inc. announced that Toshiba Corp. has deployed Magma’s Talus IC implementation software for developing ICs at 90-, 65- and 40-nanometer (nm) process nodes that target multimedia, networking and printer applications, in Toshiba worldwide design centers.

Toshiba adopted Talus after an extensive evaluation that proved the software’s ability to drastically reduce turnaround time, increase designer productivity and improve quality of results.

Toshiba deployed Magma design implementation software in Toshiba’s Apex flows in 2001, and now has finished multiple designs including 65-nm and 40-nm tapeouts using Talus through its Apex 4.0 flow.

“Toshiba has demanding delivery schedules and performance requirements, and Magma has been instrumental in enabling us to address ever-increasing design and market challenges,” said Takashi Yoshimori, Assistant Chief Technology Executive of SoC Design, Semiconductor Company, Toshiba Corp.

“Talus recently allowed us to reduce turnaround time drastically and improve leakage power and area for a multi-mode SoC design with more than 10 million gates. Based on this achievement and proven track record, we are now implementing our 90-, 65- and 40-nm designs with Talus.”

“For Toshiba and its customers, reducing turnaround time is key,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “Toshiba’s adoption of Talus firmly establishes Magma’s software as the fastest path to silicon.”

Magma's Talus enables eSilicon to implement 400-million-gate designs

SAN JOSE, USA: Magma Design Automation Inc. announced that eSilicon Corp., a pioneering semiconductor value chain producer (VCP), is completing the implementation of several very large customer designs using the Talus IC implementation system, including Talus Design, Talus Vortex and Hydra.

These designs are being implemented in a 65-nanometer (nm) process and are more than 500 sq. mm in area, with more than 400 million gates. This is the equivalent of 30 million placeable objects, including more than 100 million bits of memory and more than 2,000 memory instances.

These highly complex chips require eSilicon to use a design solution with extremely high capacity and the ability to deliver fast turnaround on design planning and implementation.

In addition, given a tight delivery schedule, eSilicon needed a system that would be usable "out of the box" without a lengthy setup cycle. Magma's field team partnered with the eSilicon design team to deploy Talus.

"We selected Talus for these large designs because of its capacity and our need to minimize our deployment time and keep the implementation cycle as short as possible," said Prasad Subramaniam, vice president of Technology of eSilicon. "The high complexity of these designs poses a significant challenge in productivity and turnaround time.

"We are pleased that the Talus multi-CPU feature works smoothly and yields significant improvement across a broad implementation flow. We have our default implementation build scripts for large blocks to use two CPUs and we increased to four CPUs for critical runs. This allowed us to gain 1.5 times to 3 times improvement in turnaround time on these large designs."

eSilicon found Talus to be well suited for these designs. Talus' underlying unified data model architecture contains the entire set of data associated with the design. The complete design data can be exported or imported at any time as a Volcano(tm), Magma's proprietary database format.

One of the eSilicon designs is based on a collaborative development model with the customer, and Talus' unified architecture simplifies the efficient handoff of design data via Volcanoes at various points during the implementation process.

In addition, Talus' core multi-CPU feature and enhanced GlassBox modeling for timing enabled very significant improvement in the turnaround times for implementation and analysis.

One key challenge for these complex chips is the turnaround times for top-level analysis and optimization. eSilicon is making extensive use of a new Hydra GlassBox abstraction capability.

This enhanced GlassBox abstraction feature yields extremely compact representations of the blocks that contain all the physical, timing and extraction data necessary for fast and accurate chip-level analysis and optimization without consuming enormous amounts of memory.

Because of this new "cached delay" feature for GlassBox abstraction, the latest Talus release requires less than 50 percent of the memory resources required by the previous Talus version and delivers up to a 5X improvement in runtime compared to the previous GlassBox approach.

"The fast deployment of Talus and implementation of these designs is a testament to eSilicon's engineering skill and demonstrates Talus' ability to handle large, complex designs," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

"The size of these designs and the speed of deployment demonstrate the major improvements in capacity, runtime and usability that have been engineered into the latest Talus release. It also validates Hydra's capability for managing the top-level design and optimization of very large designs without excessive memory consumption."

XMOS uses Magma Talus 1.1 for XS1-L1 event driven processor

SAN JOSE, USA: Magma Design Automation Inc. announced that XMOS, the leader in event driven processors, taped out its recently announced XS1-L1 XCore using the Talus 1.1 IC implementation system. XMOS upgraded to the latest version of the Magma software after early testing showed improvements in the closure of their XCore processor design.

"We benchmarked an early release of Talus 1.1 during the XS1 development program," said Mark Lippett, vice president of engineering at XMOS. "Improvements in the routing algorithms led us to migrate to the Talus 1.1 release for our production tapeout."

The XS1-L family provides embedded software developers with an energy-efficient, scalable, multi-core solution. It enables complete systems that combine interface, DSP and control functions to be built entirely in software.

Each XS1-L XCore contains a 32-bit processor and operates up to 400MIPS. XCore power consumption is below 500 microwatts in sleep mode and 20 milliwatts in standby with active power adding under 450 microwatts/MHz.

The event-driven architecture, together with XMOS' programming tools, enables XCores to switch automatically between standby and active modes, saving up to 90 percent of energy in low duty-cycle applications. The XS1-L1 is built on a 65-nanometer process. Samples are available now from www.xmos.com.

"Like XMOS, many of our other customers are implementing very complex chips and need a powerful, fast, high-quality chip design system that is also easy to use," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

"Talus 1.1 features simplified flows with fewer commands and still provides improved performance, timing closure and power optimization. XMOS' ability to deploy Talus 1.1 quickly to meet their design requirements demonstrates the advantages of Magma's COre technology."

Magma supports SMIC processes with 65nm low-power reference flow

SAN JOSE, USA: Magma Design Automation Inc. announced availability of an advanced low-power IC implementation reference flow for the 65nm process and low-leakage-process intellectual property (IP) from Semiconductor Manufacturing International Corp (SMIC).

SMIC's 65-nm logic technology combines improved performance and reduced power consumption with the increased design possibilities and cost efficiencies that a smaller-node process offers.

Magma's Talus IC implementation system fully supports the SMIC 65-nm low-leakage process intellectual property (IP), including standard-cell libraries, power management kit (PMK) and memory compilers.

The Talus implementation flow coupled with Talus Power Pro applies various techniques throughout implementation and to minimize power consumption while maximizing quality of results.

Talus reduces turnaround time and the power consumption of ICs used in a wide range of consumer applications, such as mobile phones, PMPs, global positioning, digital TV, set-top boxes and mobile storage devices.

"Magma's development of an advanced low-power IC implementation reference flow for the SMIC 65-nm process technology demonstrates both companies' commitment to providing designers with tools and technology to improve performance and reduce power consumption of ICs," said Paul Ouyang, vice president of design services at SMIC.

"Talus is the only flow that enables designers to address power considerations throughout the flow and within a single environment," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Using Talus, SMIC customers can get the best combination of performance, low power and fast turnaround times for complex designs."

The reference flow is available now at no cost to Magma customers.

Magma, Camtek team to enhance yield of advanced semiconductors

BANGALORE, INDIA: Magma Design Automation Inc. today announced that Camtek Ltd has integrated Magma’s YieldManager software into Falcon, Camtek’s flagship line of automated wafer inspection and metrology systems, and will sell it as an option.

The combination of Camtek’s automated inspection platforms and Magma’s YieldManager allows fab engineers to more effectively analyze inline defect data and yield data to accelerate root cause identification of yield problems, ensuring higher yields and reducing manufacturing costs.

Camtek systems deliver outstanding 2D and 3D capabilities in a versatile and flexible platform that meets the evolving demands of any design application. Cleanroom compatibility and compliance with factory automation standards allows Camtek systems to fit seamlessly into the most advanced production environments.

YieldManager is a customizable yield-management software system that allows engineers to collect, correlate, analyze and share critical data. YieldManager combines high-level correlation of data from disparate sources with the rapid drill-down of data scope to expedite root-cause identification of yield-limiting problems, saving engineering time and focusing resources.

The joint Magma-Camtek solution allows semiconductor fab and lab analysis teams to more quickly and easily locate potential defects and make corrections faster.

“Minimizing manufacturing costs while ensuring reliability are critical factors for semiconductor success,” said Rafi Amit, CEO of Camtek. “By enabling faster identification of yield problems, Magma and Camtek help semiconductor customers achieve their cost, performance and time-to-market goals.”

“Advanced fabs have an array of sophisticated equipment that provides engineers with an unprecedented amount of information about the IC, but analysis of the data is time consuming,” said Ankush Oberai, vice president of Magma’s Fab Analysis Business Unit.

“With YieldManager software and the Falcon systems, designers can more quickly and efficiently leverage the information from the automated wafer inspection system to make changes in the IC manufacturing process that enhance yield.”

Magma's Talus-based RTL-to-GDSII low-power reference flow for UMC's 40nm process

SAN JOSE, USA: Magma Design Automation Inc. announced the availability of an integrated low-power IC implementation reference flow for UMC's advanced 40-nanometer (nm) process.

This reference flow supports the UMC 40-nm process and the UMC 40-nm low-leakage library. Based on the Magma Talus IC implementation system and fully compliant with the Unified Power Format (UPF), it allows designers to address low-power nanometer design considerations during implementation and within a single environment, maximizing quality of results (QoR) while reducing turnaround time. Similar low-power reference flows for 90- and 65-nm processes are already available from Magma.

"UMC and Magma's long-standing partnership has resulted in many productive design support solutions for our customers," said Stephen Fu, director of the IP Development and Design Support Division at UMC. "Our latest effort is an integrated low-power IC implementation reference flow that gives designers a means to address low-power issues during the implementation phase of 40-nm designs."

"Our goal in working with UMC was to give project teams a way to address low-power nanometer design considerations with an integrated low-power IC implementation reference flow," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The Talus platform's unique integration accomplishes that goal while reducing overall turnaround time."

Magma-UMC low-power reference flow
The Magma-UMC RTL-to-GDSII low-power reference flow includes the required scripts and documentation for Magma users to move to UMC's advanced 40-nm low-power process technology and offers timing closure without iterations to enable quick silicon delivery.

A multiple-power domain is used to create different voltage domains with designated purposes, including reducing leakage current and reducing chip power consumption while meeting timing requirements. The reference flow provides MTCMOS power switch insertion and placement for implementing a switched domain.

It performs automatic checking and insertion of level shifters and isolation cells into the right locations in a domain, insertion of retention flip-flops in the domain that can be powered down, and always-on buffering for retention of the control signal in the switched domain.

In addition, Magma's placement engines complete all the standard-cell placement in the design using features such as comprehensive congestion analysis and timing-driven placement.

Magma's clock tree synthesis constructs a minimum-skew clock tree. With the GUI clock-tree browser, users can monitor the clock tree implementation during the flow and can select the correct clock tree structures for their design. After clock tree synthesis is completed, Magma's advanced routing engines complete the routing, including signal and power routing, based on UMC's 40-nm design rules.

Magma's integrated IC implementation solution and unified data structure as the basis for the reference flow ensures better quality results for timing, area, power, signal integrity and reliability while minimizing the design cycle.

The reference flow is available from Magma now at no cost to Magma customers.

Magma's Talus Vortex and Hydra deliver timing closure on tough STARC design

SAN JOSE, USA & YOKOHAMA, JAPAN: Magma Design Automation Inc. announced that Japan's Semiconductor Technology Academic Research Center (STARC) has evaluated the Talus Vortex physical implementation system and Hydra, an auto-interactive floorplanning and hierarchical design planning and management solution.

STARC, a research consortium co-founded by major Japanese semiconductor companies, reported that the combined Talus Vortex and Hydra flow delivered impressive timing closure results on a very large test design and noted that the use of multi-processing throughout the flow contributes to the good turnaround time.

Based on the these results, STARC is presenting Talus Vortex and Hydra to member companies as a complete hierarchical flow to manage multimillion-gate design complexity and achieve timing closure.

The decision to endorse Magma's tools was made after a competitive benchmark based on a hierarchical design that included 12 million logic gates, 1,147 memory macros and six hierarchical blocks targeted at the 45nm process. The benchmark was meant to test the tools' ability to reach timing closure with no timing or design rule check (DRC) violations in the shortest amount of time.

Talus Vortex and Hydra reached timing closure with no DRCs and good turnaround time given the size of the design and the multi-mode, multi-corner optimization required to complete the design.

Magma's logic optimization capabilities reduced congestion and yielded an implementation that was much easier to route. This, along with Magma's crosstalk-avoidance capability during routing, reduced chip area by more than 12 percent, a significant achievement.

"We were impressed with the performance of Magma's Talus Vortex and Hydra on this large, complex 45-nm design," said Nobuyuki Nishiguchi, vice president and general manager of Division 1 at STARC.

"The Talus Vortex and Hydra multi-processing capabilities and large design capacity work well on large hierarchical designs. We were equally impressed with the system's ability to reach timing closure while optimizing for 15 different multi-mode, multi-corner scenarios."

"Ensuring that complex ICs operate correctly across all design modes and are 100 percent reliable across all process corners is an increasingly difficult task," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

"With Talus Vortex's native multi-mode and multi-corner capabilities, analyses are performed earlier in the flow, use less memory and offer better runtime. The results of the STARC evaluation demonstrate Talus Vortex's ability to meet the timing, area and turnaround time of today's most advanced designs."

Magma's Vivek Raghavan is new MD, India Operations

BANGALORE, INDIA: Magma Design Automation Inc. today announced the appointment of Vivek Raghavan as Managing Director of the company's India operations.

Raghavan will report to Roy E. Jewell, Magma President and Chief Operating Officer, as well as continue his current responsibility as Vice-president of Magma's Custom Design Business Unit, managing development of physical verification products.

“India is a key part of Magma’s overall strategy and we are looking to Vivek to continue working with our team there to expand the company’s role in India’s EDA fabric,” said Rajeev Madhavan, Magma’s Chairman and Chief Executive Officer. “He has been one of our senior managers in India and I expect he will work with our talented employees to continue the India operation’s success.”

Nearly 30 percent of Magma’s worldwide workforce operates in the company’s Bangalore, Mumbai and Noida facilities.

“Recent developments in Magma products demonstrate great technology and strong competitiveness," Raghavan said. “I’m very pleased to continue working with the team in India that has helped make these advancements possible.”

Vivek joined Magma in 2004 when it acquired Mojave Design, where he was Co-founder & CEO. Prior experience includes senior engineering management positions with Synopsys and Avant! Corporation, where he developed and managed successful products in physical design and parasitic extraction of integrated circuits. He holds a B.Tech degree in Electrical Engineering from IIT-Delhi and a Ph.D. in Electrical and Computer engineering from Carnegie Mellon University.