Showing posts with label VCS2009. Show all posts
Showing posts with label VCS2009. Show all posts

Tuesday, 26 May 2009

Exar selects Synopsys as leading EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Exar Corp., a leading provider of analog and mixed-signal solutions for connectivity and power management, has signed an expanded business agreement to establish Synopsys as its leading EDA partner.

As a result of the new multi-year agreement, the Synopsys' Galaxy Implementation and Discovery Verification platforms will be Exar's key design environment for designs at 65nm and below.

"We conducted an extensive evaluation process to select an EDA partner to not only support our current project needs, but our future design horizon as well, and Synopsys was the clear choice," said George Apostol, senior vice president and CTO, Exar.

"Over the years, Synopsys has demonstrated the technology leadership and outstanding technical support that is vital to helping us deliver highly differentiated silicon solutions to our customers. Synopsys tools, especially for mixed-signal designs, are ideal for our forthcoming data communications, storage, interface and power management products."

With the most recent agreement, Exar has chosen products that span Synopsys' broad portfolio. These products include Synopsys' Galaxy implementation platform featuring IC Compiler place-and-route technology, Design Compiler Graphical synthesis, PrimeTime PX timing and power analysis, PrimeRail power network analysis, Star-RCXT parasitic extraction, Hercules physical verification, TetraMAX automatic test pattern generation, and DFT MAX adaptive scan compression; Synopsys' Discovery verification platform featuring the VCS, HSPICE, HSPICE RF and CustomSim simulators for analog and digital verification, MVRC static voltage-aware verification, and MVSIM voltage-aware simulation; and DesignWare Library IP.

"Companies like Exar succeed through their ability to create highly differentiated designs and are justifiably selective when it comes to the partners with whom they entrust their design flows," said John Chilton, senior vice president of Marketing and Strategic Development at Synopsys. "Synopsys welcomes the opportunity for a long-term partnership with Exar, and we look forward to helping them further distinguish their products through technical innovation and rapid market introduction."

Tuesday, 12 May 2009

Toshiba selects Synopsys as key EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Toshiba Corp. has signed a multi-year business agreement to establish Synopsys as its key EDA partner across the Toshiba semiconductor design flow.

As a result of the expanded relationship, Toshiba Corporation plans to expand use of Synopsys' verification and implementation design flow while partnering to reduce design cycle time.

"For longer than five years we have continued to build a successful relationship with Synopsys by collaborating across a broad set of next-generation EDA, commercial IP, and manufacturing technologies," said Tomotaka Saito, senior general manager of System LSI Division, Semiconductor Company, Toshiba Corp.

"The resulting products and design flow have enabled Toshiba to tape-out a number of chips across multiple technologies. Our existing Synopsys relationship helps solve current and future SoC design needs," he added.

The latest agreement between the two companies expands Toshiba's use of solutions across Synopsys' comprehensive portfolio. These products include Synopsys' Galaxy design platform featuring IC Compiler place-and-route technology, Design Compiler synthesis, DFT MAX test synthesis, TetraMAX automatic test pattern generation, PrimeTime timing analysis, Star-RCXT parasitic extraction, and IC Validator physical verification; Synopsys' Discovery™ verification platform featuring the VCS, HSPICE and CustomSim simulators for analog and digital verification; DesignWare Library; the Synplicity FPGA design solution; and the Eclypse Low Power Solution.

"Toshiba and Synopsys share many common goals, including pioneering high technology to develop products that create excitement," said Aart de Geus, chairman and CEO of Synopsys. "Synopsys greatly appreciates the long-standing collaboration with Toshiba that has resulted in numerous technology innovations deployed across consumer applications from digital TVs and mobile handsets to CMOS image sensors. By deepening our partnership, Synopsys intends to help advance Toshiba's technology strengths and increase R&D efficiency by reducing their design cycle time."

Friday, 1 May 2009

Verivue deploys VMM and Synopsys VCS solution

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Verivue, Inc. has standardized on the production-proven VMM verification methodology and VCS functional verification solution, both key components of Synopsys' Discovery Verification Platform, for the verification of their flagship product, the MDX 9000 Series Media Distribution Switch.

The VMM-based approach allows Verivue to implement a transaction-based verification methodology that provides reusable test environments for higher test coverage, ease-of-use and scalability from block to system-level. The combination of the VCS solution and VMM enables faster turn-around with accelerated compile times and optimized performance for system designs, contributing to a productivity boost of up to 4x over traditional approaches.

A major benefit of VMM-based verification environments is verification reuse. With VMM, Verivue is able to create fifteen "plug-and-play" transaction models that can generate large volumes of data. Engineers are able to boot the entire system as soon as the hardware becomes available. Additionally, the VMM Applications, such as Register Abstraction Layer (RAL), speed up and simplify verification.

"With hundreds of successful deployments in highly complex verification environments, VMM is the most widely used verification methodology," said Swami Venkat, senior director of Marketing in the Verification Group at Synopsys. "Engineers using VMM and VMM Applications consistently achieve higher quality verification results and greater verification productivity, as evidenced in a large number of VMM user papers and tape-outs. Synopsys continues to invest in verification methodology innovations with new technologies such as the VMM for Low Power to address complex functional verification challenges."

Thursday, 30 April 2009

Tego standardizes on VMM and Synopsys VCS Solution to speed RFID tags verification

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Tego, Inc. has standardized on the production-proven VMM verification methodology and VCS® functional verification solution, both key components of Synopsys' Discovery Verification Platform, to verify its radio frequency identification (RFID) tags for the aviation industry.

Tego's RFID tags, which are used to store intelligent data directly on an object without the need for battery power, have grown increasingly complex due to memory limitations and, therefore, require a robust verification solution to accelerate the design cycle. Tego chose a VMM-based approach to address the increased chip complexity, higher test volume and ease-of-use requirements. They have also standardized on the VCS solution to optimize performance, bug detection and capacity. The combined solution enabled Tego to achieve first-pass silicon success on its next-generation passive RFID tag and will help the company to hit ever-narrowing time-to-market windows on future projects.

A major benefit of VMM-based verification environments is easier customization. With VMM, Tego is now able to create a customized, "plug-and-play" testbench environment that can run data collection and comparison separately. Engineers are able to generate specific corner scenarios or collect functional coverage for particular test scenarios and generate new test cases without having to modify the entire testbench unnecessarily. Additionally, the VMM-based environment allows reuse of the pre-existing golden reference model, initialization routines and protocol-dependent monitoring logic, improving productivity and streamlining time-to-market for future designs.

Wednesday, 8 April 2009

Synopsys on Discovery 2009, VCS2009 and CustomSIM

If you've been following the EDA industry closely, you'd be well aware of three major announcements by Synopsys over the last couple of days. These are:

* Synopsys introduced the Discovery 2009 verification platform, delivering faster, unified verification solutions.
* It unveiled the VCS multicore technology, delivering 2x verification speed-up.
* It introduced the CustomSim Unified Circuit Simulation solution, which addresses custom digital, analog and memory verification challenges.

I met up with Dr. Pradip K. Dutta, Corporate Vice President & Managing Director, Synopsys (India) Pvt Ltd and Manoj Gandhi, vice president and general manager, verification group @ Synopsys, in an attempt to understand how significant these announcements are for verification.

Verification is huge!
According to Manoj Gandhi, at the macro level, design complexities continue to grow. As this grows, one big challenge is verification. The reason is: today's SoC designs and large IC designs, they are being approached like large software projects.

He said: "Verification becomes huge, like software. It is expensive in hardware design. We focus on the verification challenges. We introduced the System Verilog about four to five years ago, and we had also acquired ArchPro. Yesterday, we announced the Discovery 2009, CustomSim and VCS2009."

How can users make use of new CPUs coming out? "We aim to get higher much performance using multicore architecture," he added.

Introducing VCS2009
The VCS2009 is multicore enabled, runs the industry's first low-power verification methodology, and enables fastest mixed-signal simulation with the CustomSIM. Focusing on the VCS2009, Gandhi said: "In verification, there's a design under test and verification. A lot of designs now have multicores. AMD is among the many folks using the VCS2009. Almost every CPU is designed using VCS. It plays a big role in large SoCs."

Design companies have several activities such as test bench, debug, etc. All of these can now be parallelized. "Customer designs can be simulated on multiple threads," Gandhi said. "Also, the applications can also be simulated on different threads, called application level parallelism. We can actually bring about 5-7X improvement in verification with the VCS2009."

According to him, this product is already being used by some large customers. "This is our next phase of performance innovation. The processor roadmap is getting more and more multicore. We have over 200 customers," he added.

The VCS distributes time consuming activities across multiple cores. Gandhi added that each core has a lot of computations. You may do lot of parallel activities with the mobile phones. All activities are now in parallel.

And how about the speed-up from parallel computation with the industry-leading Native Testbench (NTB)? He said: "We were one of the first to introduce all technologies as part of a single compiler. That brought the 5X speed-up. We did all of this in verification, and a test bench core was brought into verification."

The combination of DLP and ALP optimizes VCS performance over multicore CPUs. Design level parallelism (DLP) and application level parallelism (ALP) -- all CPUs can be threaded on different cores.

Low-power verification methodology published
Synopsys has published a book on industry's first low-power verification methodology, along with ARM and Renasas. It is an attempt to bring technology to the mainstream -- how to do low-power verification. There are other 30 companies who participated in this exercise.

On the CPF vs. UPF debate, he said that UPF is a standard where Magma, Mentor, Synopsys, etc. have participated. Cadence has CPF. Users can make use of this book and apply, on top of both UPF and CPF.

Introducing Discovery 2009
According to Synopsys, this solution is doing very well in the market. The company has seen strong technology leadership over the last two to three years. It has also created strong investments.

CustomSIM is a unified circuit simulation solution. "We have a software to silicon verification focus. We are all the way from system level design to RTL, to software verification, etc. Discovery has some technologies as part of that, noted Gandhi.

What has Synopsys done right?
A most interesting point in the EDA industry, I feel, has been the performance of Synopsys, in an otherwise difficult segment over the past year. So, what are the reasons behind this success?

Gandhi added: "Our management are all strong technologists. We have invested tremendously in bringing in strong technology leaders. In India, many companies needed R&D collaborations locally. For us, it was a big win when we invested in Bangalore. We work closely with customers delivering technologies that will address challenges two-three years from now.

Dr. Pradip Dutta elaborated: "Synopsys is very strong in product leadership (PL). The other two key areas are customer intimacy (CI) and operational excellence (OE). You need to be highest in PL. We have been very conservative even during strong times."

That is indeed a marvellous thought! Those who are typically strong in technology, generally go on to develop great intimacy with customers, and all of this starts reflecting on their operations, which are anyway excellent! Here's a message for those who wish to do well in tough times -- strong product leadership, coupled with customer intimacy and well, corresponding operational excellence!

Focus on verification
Now that the focus is quite clearly on verification, how do EVE and the other verification companies stand out? EVE is currently in the emulation space. Gandhi added that EVE competes more wtih Cadence and Mentor. "We work with EVE on many accounts. Verification is all about finding bugs. Emulation has been more cyclical."

According to him, Synopsys is now looking at tackling the next level -- how do you reduce the overall cost? "We will go beyond selling tools. We would look at how to identify issues and saving verification costs." I believe, verification takes up close to 70 percent of an overall design test.

Commenting on the EDA industry in India, both, Dr. Dutta and Gandhi feel it is still buzzing quite well, despite what's been happening in the global context. "We have invested quite a lot. We have a large team here. We continue to collaborate with local institutions here as well," Dr. Dutta added.