eASIC announces new ASIC-in-a-box design kits

SANTA CLARA, USA: eASIC Corp., a provider of NEW ASIC devices, announced the immediate availability of two ASIC-in-a-Box design kits that enable ASIC design to be widely accessible and thereby reverse the trend of declining ASIC design starts.

Through simplifying the design flow, the design kits empower engineers who are unfamiliar with ASIC design to now complete designs at a fraction of the cost and time compared to traditional standard cell ASICs.

Nextreme NEW ASICs are uniquely constructed to help simplify design, verification and silicon processing steps within the overall flow. Designers are able to focus their effort mainly on achieving their desired functionality and timing and not on arduous complex tasks such as power mesh design, signal integrity, test insertion, clock insertion, STA, ATPG, formal verification and LVS/DRC as they do with traditional standard cell ASICs.

The NEW ASIC-in-a-Box design kits provide software and documentation for completing and implementing Nextreme chip designs, and also deliver board design and debug guidelines for designing systems that incorporate Nextreme devices.

“Our NEW ASIC-in-a-Box design kits dispel the myth that ASICs are difficult, risky and expensive to design,” commented Jasbinder Bhoot, Vice President of Marketing at eASIC.

“eASIC has completed over 100 tape outs and delivered over 100 prototype designs in less than two years using the flow and tools that are now available in the ASIC-in-Box kits. Our new design kits make ASIC design affordable, accessible and achievable for everyone.”

Design kit contents
The NEW ASIC-in-a-Box Design Kits contain the following items:

* eASIC’s eTools software suite that includes easy to use utilities for configuring PLLs/clocks, assigning pins/pads, generating memories and post placement configuration and DRC.
* Magma DA’s Blast RTL software for performing synthesis and placement.
* Documentation and design tutorials to accelerate design implementation.
* JTAG programming cable for configuration and debug.
* Technical support website access.

Key ASIC acquires Taiwan's ASIC firm Gateway Silicon

SANTA CLARA, USA & KUALA LUMPUR, MALAYSIA: Key ASIC Berhad has signed a definitive agreement with the shareholders of Gateway Silicon Inc. (GSI) to acquire up to 100 percent of the company in a cash transaction.

GSI is a subsidiary of Macronix International Co. Ltd. a semiconductor IDM headquartered in Taiwan. Macronix ended calendar year 2008 with revenues of NT$23.28B or approximately $710M.

Gateway Silicon is a professional IC design service company founded in August 2006 in Hsin Chu Science Park, Taiwan. GSI focuses in research and development of analog and digital IP for consumer ICs. GSI has developed a significant portfolio of analog and memory IP focused in the graphics and video applications.

GSI provides SOC implementation and IC turnkey design services. Through GSI’s proprietary platform solutions, competitive cost structure, and integrated turnkey services, customers benefit from high quality IC products developed and delivered on schedule to meet the customer’s time-to-market requirements. GSI has offices in Japan and Taiwan.

“Key ASIC is a leading player in the ASIC design industry. We are pleased to merge with Key ASIC to build a bigger and stronger company that will enable all of us to play a more significant role in the ASIC design business. Key ASIC has very strong design experience in advanced technologies such as 65nm and 45nm, and this will be a big value add to GSI’s existing customer base,” said J.P. Peng, CEO of GSI.

“We have built up a very rich portfolio of analog IP blocks and we have a very strong analog circuit design team that will be a valuable asset to the combined entity,” he added.

“We share the same vision with the key shareholders of GSI in building a strong ASIC design business for consumer and communications applications globally. This merger is a synergy of two companies with complementary skills and technologies. This merger will enable us to expand and better serve our customers,” said Eg Kah Yee, Chairman of Key ASIC. “This strategic exercise is in line with our growth plans,” he added.

With this acquisition, Key ASIC expands its position in the ASIC markets of Japan and Taiwan. This acquisition is expected to bring high growth in 2010 and beyond. Key ASIC expects to accelerate its growth through additional synergistic mergers and acquisitions.

Atmel's SiliconCity for low-cost custom defined SoCs

SAN JOSE, USA: Atmel Corp. announced a new custom architecture for 90nm SiliconCity ASIC development, providing up to 350K gates/mm2, offering customers gate densities in the range of a standard cell ASIC.

SiliconCity Flexible Architecture allows designers to create their own unique base wafer architecture for multiple product variations while generously reducing customer design time, lowering the NRE and reducing risk through design reuse.

ASIC development based on the architecture allows for lower mask fees and faster time to market. "Consider the fabless semiconductor company that has multiple products defined, all with slightly different features," said Jay Johnson, Marketing Director for Atmel's NA ASIC Business.

"Creating a new ASIC for each one is too costly and time consuming. The old trick of multiple products on the same die with different bond options has run out of gas. That's the real value of SiliconCity Flexible Architecture."

The architecture relies on the breadth of Atmel's standard microcontroller solutions, to create SoCs including the reusability and proven IP that Atmel offers through its AVR and AT91SAM standard products.

Metal Programmable Cell Fabric (MPCF) at the heart of the technology: MPCF is Atmel's patented ASIC technology that makes the CAP (customizable microcontroller) family of products, and SiliconCity Flexible Architecture, possible.

In the case of CAP, Atmel defines the platform with ARM cores and bus subsystems, peripherals and memories. SiliconCity Flexible Architecture leaves the definition of the platform up to the user.

By predefining the common embedded core and bus, memory and peripheral mix, the customer has the ability to implement unique IP for multiple products. The architecture gives the customer complete control, while MPCF gives it the flexibility.

MPCF offers a smaller core cell with better routing. The key to the MPCF technology is a 6 transistor core cell that is less than 3.2 square microns. In the 90nm process, a SiliconCity Flexible Architecture ASIC yields between 300,000 and 350,000 gates per square millimeter.

A novel routing scheme provides two layers of metal for interconnect, increasing gate utilization up to 90 percent. The combination of the higher gate density and better routability of MPCF-based SoC results in die sizes that are about half those of previous 130nm generations.

Routing and transistor geometry alignment: With MPCF, the cell size is matched perfectly to the integer multiple of the routing grid and transistor pitch, which results in no wasted silicon.

In addition, contacts and vias are also the same size as metal trace, which eliminates any potential overlap and provides the most effective vertical use of silicon in the design.

These aspects of MPCF make targeting the exact gate size required for the design much easier and more cost effective than the typical sea-of-gates architecture common with gate arrays and some early structured ASIC products.

In addition, MPCF metal-programmable cells and standard cells can be placed in separate regions on the die or freely mixed without any die size penalty. Therefore the fixed platform part of the design can be implemented in standard cell technology, while the flexible portion of the die with MPCF for quick derivative spins.

Easy migration from existing processor-plus-FPGA designs: Many existing designs based on an industry standard microcontroller and an FPGA may be directly migrated to a SiliconCity Flexible ASIC in as little as 20 weeks from final gate-level netlist with minimal re-engineering and low initial NRE mask charges.

Future iterations of designs can be implemented in just 8-12 weeks with even lower single metal mask NRE charges.

Products based on the 90nm SiliconCity Flexible Architecture are available now. It is also available in 130nm.

Semico releases two reports on ASIC design starts

PHOENIX, USA: Semico Research Corp. has just released two reports that provide both an historical analysis and forecasts the future of ASIC design starts.

The current global economic slowdown is having an adverse impact on design starts for ASICs. The slowing of design start activity began at the end of 2008 and is continuing through 2009. Semico believes design activity will recover back to more historical norms in 2010.

The “ASIC Design Starts: Changes in Industry Dynamics” report provides an in-depth perspective by showing a comparison between design starts for SoCs and all other types of ASICs.

This report also examines the continuing increase in SoC design costs. ASIC design starts data show changes in design for each device type including analog, mixed signal, gate array, PLD, FPGA, performance SoC, value SoC and structured ASIC.

The design starts data is further segmented by: product type, process geometry, gate count and geographic region. This report contains a wealth of data in 55 tables and 58 figures/graphs.

The “ASIC Design Starts: By Key Applications Revisited II” report segments the data by 66 of the key end applications that drive the design starts market within the computing, communications, consumer, transportation and industrial segments. Within each end application, the data is further segmented by: Analog, Mixed Signal, Performance and Value SoC, PLD, FPGA, Gate Array and Structured ASIC. This report contains an enormous amount of data in 134 tables and 69 figures/graphs.



Both reports complement each other. For each segment, they include design starts and the ASIC unit volumes associated with those design starts. While they use the same worldwide design starts information, each report analyzes the data from a different perspective.

MOSAID sues IBM for patent infringement

OTTAWA, CANADA: MOSAID Technologies Inc. announced that it has initiated litigation against IBM Corp. of Armonk, New York, for infringement of six of MOSAID's United States patents. The suit was filed today in the United States District Court for the District of Delaware.

In its complaint, MOSAID claims that IBM has infringed and is infringing MOSAID's patents by making and selling microprocessor and Application Specific Integrated Circuit (ASIC) products, which practice MOSAID's patents. MOSAID is claiming infringement of U.S. Patent Nos. 6,603,703; 6,580,654; 6,980,448; 7,038,937; 7,486,580; and 7,535,749. The patents were granted on MOSAID's fundamental Dynamic Random Access Memory (DRAM) circuit inventions.

"We are taking this action to protect our intellectual property because we have been unable to reach a reasonable settlement with IBM, despite many years of negotiation," said John Lindgren, President and CEO, MOSAID.

"We believe that IBM requires a license to our patents for its microprocessor and ASIC products that contain embedded DRAM. MOSAID has licensed virtually 100% of the global commodity DRAM industry, including signing patent license agreements covering embedded DRAM products. The value of our patents is internationally recognized."

MOSAID is represented by Howrey LLP, a top US law firm specializing in trademark and patent litigation.

MIPS, EE Solutions bring MIPS architecture to China and Taiwan semicon firms

SUNNYVALE, USA & HSINCHU CITY, TAIWAN: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for home entertainment, communications, networking and portable multimedia markets, and EE Solutions, a leading provider of ASIC and SoC design solutions, are teaming to provide semiconductor companies in China and Taiwan with easy access to MIPS' industry-standard technology.

EE Solutions licensed the synthesizable MIPS32 24KEc core as part of its digital IP portfolio and will work with MIPS to provide value-added solutions to joint customers.

EE Solutions has developed a hardened 24KEc core in TSMC 65nm process technology, resulting in proven expertise that it can leverage in engagements with customers. With MIPS' high-performance, low-power 24KEc core and design and turnkey services from EE Solutions, customers designing SoCs for multimedia devices such as set-top boxes, DTVs, and digital still cameras can get to market quickly at the lowest possible cost.

"We are pleased to work with MIPS Technologies, the leader in processor IP for many multimedia markets, to provide value to our joint customers across China and Taiwan. Together we can offer solutions that result in high-performance products with smaller die size-leading to reduced development costs. Customers can benefit from MIPS Technologies' industry leading technology and EE Solutions' proven record of providing customers with the ideal solutions to achieve their business objectives," said Jim Su, president, EE Solutions.

"Through this agreement with EE Solutions, a well-respected design services firm for the Greater China market, we are enabling companies across the region to get their differentiated products to market quickly," said Art Swift, vice president of marketing for MIPS Technologies. "EE Solutions' deep experience, engineering excellence and proven track record make them a trusted and important partner for MIPS. This agreement is yet another step in broadening access to the MIPS architecture in Greater China."

MIPS32 24KE family
The MIPS32 24KE core family leverages the high performance 24K microarchitecture while incorporating the MIPS DSP Application Specific Extension (ASE). These instructions provide signal processing performance of up to 3x over a range of embedded applications compared to RISC implementations without the DSP ASE. The 24KE family provides very efficient DSP capability while significantly reducing overall SoC die area, cost and power consumption.

The 24KEc core is a high-performance, low-power, core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.

eASIC, IPextreme announce Freescale ColdFire processors for Nextreme NEW ASICs

SANTA CLARA, USA: eASIC Corp., a provider of NEW ASICs devices, and IPextreme, the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, announced the immediate availability of Freescale’s 32-bit V1 and V2 ColdFire processor cores for Nextreme NEW ASICs.

The addition of the ColdFire processors to eASIC’s eZ-IP core library, enables designers to implement small foot-print, ColdFire cores on fast turnaround Nextreme NEW ASICs and thus provide a low-cost entry point for creating customized ColdFire-based applications within consumer, medical, automotive, and industrial markets.

With almost three times greater performance of comparable implementations in low-cost FPGAs, Nextreme NEW ASICs provide system designers with a significantly better price/performance alternative to FPGA implementations and with a much lower up-front cost alternative to standard cell ASIC implementations.

The 32-bit RISC V1 and V2 ColdFire processors are backed by a complete and proven ecosystem of development tools, software stacks, and drivers from Freescale and other leading providers such as GNU, Green Hills Software, Wind River Systems, Accelerated Technology / Mentor Graphics, and many others.

“The inclusion of V1 and V2 ColdFire processors into our eZ-IP portfolio enables embedded system designers to leverage their existing code-base while quickly delivering optimized, highly differentiated, low-cost solutions that can be taken into high-volume production,” said Jasbinder Bhoot, Vice President of Worldwide Marketing at eASIC. “We want our customers to have the freedom to choose the right processor core for the task at hand, and not forced into a proprietary offering as we see with some FPGA vendors,” added Bhoot.

“The V1 and V2 ColdFire synthesizable IP cores are two of our most popular processors and we are excited to add them to eASIC’s eZ-IP core library,” said Rick Tomihiro, Vice President of Marketing at IPextreme. “Thousands of embedded systems designers worldwide create designs around the ColdFire architecture and enabling them to combine the high performance, low gate count and complete ecosystem of ColdFire microprocessors with the low cost and high performace of eASIC’s Nextreme NEW ASICs provides them with a unique advantage over their competition to create advanced and low cost embedded solutions to meet and exceed their customers requirements.”

Deliverables
The V1 and V2 ColdFire cores for the Nextreme NEW ASICs are available from IPextreme. The cores are delivered in Verilog source RTL and include:

* Synthesizable Verilog source code.
* Integration testbench and tests.
* Documentation.
* Scripts for simulation and synthesis with support for all common EDA tools.

ARM uses eASIC devices to validate Cortex-A9 MPCore multicore processor-based devices

SANTA CLARA, USA: eASIC Corp. a provider of low up-front development cost NEW ASICs, announced that ARM has successfully validated its next-generation Cortex-A9 MPCore multicore processor using eASIC’s Nextreme NEW ASICs.

With Nextreme, ARM was able to perform at speed verification with significantly higher performance, and lower development cost compared to the high-end FPGA solution that was previously used.

The Cortex-A9 MPCore multicore processor is the latest in a strong portfolio of CPU cores now being designed-in across wireless, networking, consumer and home applications.

The processor core integrates proven ARM® MPCore technology along with further enhancements to simplify and broaden the adoption of multi-core solutions and extending peak performance to unprecedented levels, while reducing power consumption at the processor and system level. Nextreme’s fast logic fabric, dedicated memories and single Via-based interconnect were able to provide the performance required to fully test the new Cortex-A9 processor.

“We were able to develop our eASIC device in a reduced time and cost of a standard cell ASIC and with development costs that were even lower than an FPGA approach and the eASIC device worked right first time on our PBX-A9 validation and development board,” said John Goodacre, Director, Program Management of ARM Processor Division. “We see the 90nm Nextreme eASIC technology as a very cost effective way of validating and demonstrating new products to our customer base and getting them to market much earlier.”

“In addition to the growing acceptance from traditional FPGA and ASIC users, we also see considerable interest from conventional ASSP companies and IP providers who see eASIC technology as a way of developing at speed verification solutions that can even be taken into volume production,” said Jasbinder Bhoot, Vice President of Marketing, eASIC Corporation. “As process geometries shrink, eASIC will become one of the few practical solutions to perform at speed verification of IP cores and ASSPs.”

TriQuint, ZTE sign $50M agreement at US-China Business Forum

HILLSBORO, USA: TriQuint Semiconductor, a leading RF product manufacturer and foundry services provider, has signed a framework agreement with ZTE Corp.

The document states ZTE will procure TriQuint components, including but not limited to CDMA, GSM, and WCDMA ASICs, in the value of no less than $50 million dollars in CY 2009.

The agreement was formalized at the US-China Business Signing Ceremony: Partnering for Sustainable Economic Growth, April 28, 2009, in Chicago, IL. The event, aggregating $5.7 billion of US-China business through 28 contracts, was organized by the China Chamber of Commerce for Import & Export of Machinery and Electronic Products.

“We were delighted to be invited by ZTE to this event supporting international relations, and look forward to working with ZTE to further wireless communications,” said Ralph Quinsey, President and CEO of TriQuint Semiconductor. “Not only does this agreement strengthen the relationship of the two companies, but our innovations will bring high quality voice, data, and video communications to people everywhere.”

Market for key system semiconductors set for recovery

EL SEGUNDO, USA: After seeing its revenue fall by nearly one-third over the past six months, the global core silicon market appears to have hit bottom, with sequential growth set to resume in the third quarter, according to iSuppli Corp.

Global core silicon revenue is set to rise to $19 billion in the third quarter, up 8.3 percent from $17.6 billion in the second quarter. This will mark the first sequential rise since a year earlier, in the third quarter of 2008, when revenue increased by 6.7 percent.

The figure presents iSuppli’s forecast of global quarterly core silicon revenue.*Core silicon is comprised of Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs) and Programmable Logic Devices (PLDs).

Core silicon semiconductors are the key chips that implement the specific, individual functionality in an electronic system—that is, the Integrated Circuit (IC) that makes a DVD player a DVD player, and not some other type of system. In the core silicon category, iSuppli includes ASICs, ASSPs and PLDs.

“The current downturn is fundamentally different from any previous semiconductor cycle,” said Jordan Selburn, principal analyst for core silicon at iSuppli. “This cycle is driven by forces external to the chip industry, primarily the global economy, that are impacting both business and consumer spending. It’s unclear even to economic experts and financial czars when the various bailouts and reductions in interest rates will turn the global economy around.”

However, there are clear signs of a resumption in demand for core silicon.

“Core silicon suppliers are experiencing increasing demand from some of the market’s largest application drivers,” Selburn said. “The core silicon market hinges on a few major applications for most of its revenue. While some areas, most notably desktop PCs and 1G/2G mobile handsets, now are forecast to actually suffer a decline in unit shipments from 2008 to 2009, others, such as 3G wireless phones, netbook PCs and set-top boxes, are still expected to grow despite the crippled economy. These markets alone will be enough to keep the core silicon market moving down the tracks toward an expected expansion in 2010.”

Bottom’s up
The second quarter will mark the low point for the core silicon market during the current downturn. Revenue in the second quarter is set to decline by 33.9 percent from $26.6 billion in the third quarter of 2008.

While the return of sequential growth is an encouraging sign for the market, a more important metric is year-over-year growth, i.e. comparing quarterly revenue with the same period a year earlier. The core silicon market is not expected to resume quarterly year-over-year growth until the first three months of 2010. When this occurs, it means the core silicon market will be set to achieve annual revenue growth.

After a 24.2 percent decline in 2009, revenue will bounce back to double-digit growth in 2010, with a 10.1 percent increase for the year.

Positive signs ahead
The electronics industry is giving other indications that a real recovery in demand is afoot.

One of the latest positive signs is the recent announcement that the China Purchasing Manager’s Index (PMI) has rebounded to about the 50 percent level, indicating that in that country at least, the purchasing managers believe that we are already headed back into a period of expansion. The PMI in other countries has not yet surpassed the 50 percent mark, but the data from China certainly adds another few lumens to the light at the end of the tunnel.

Cautiously optimistic
It is possible that the timing of the core silicon recovery could be delayed if the economy degrades beyond current expectations, Selburn warned.

“However, This scenario seems unlikely, and the current signs of optimism—at least optimistic in relation to the past six months—are lighting the way toward the end of what remains a very gloomy, dark tunnel,” Selburn observed.

Programmable imperative: Changing semicon landscape!

This post is based on a presentation recently made by Amit Dhir, Senior Director, Business Operations, Xilinx, prior to the launch of the Xilinx Virtex-6 and Spartan-6 FPGA families. Xilinx was very kind to share this with me, and I need to thank him and Neeraj Varma, Country Manager - Sales (India/ANZ) for Xilinx.

Xilinx's next-generation FPGA families are said to enable new, targeted design platforms. Incidentally, Altera, too, decided to launch its Stratix IV GT and Arria II GX FPGAs, the same day as Xilinx.

Back to Dhir's discussion on the programmable imperative and a changing semiconductor landscape! According to him, the key market trends changing the technology landscape include the empowered consumer, hyper-connectivity and social networking. In this scenario, time-to-market and flexibility are the key attributes for success.

Customer challenges today revolve around doing more with less, and now! Companies now need to monitor their market and competitive leadership, time-to-market and profitable growth, spiraling development cost, and risk aversion and product complexity. Business constraints are now forcing customers to reduce internal R&D investments. The graph shows the IC cost by process nodes.
Time for programmables NOW!
The time for programmables is now! It is an ideal technology to help combat customer challenges. The programmable imperative is driven by factors such as market forces, financial constraints and technology drivers. Really, it all boils down to accelerating the programmable imperative!

Looking back at the logic IC landscape, business dislocation has been underway for the incumbents. From 1998 through 2004, a significant amount of IP migrated from system OEMs to ASSP vendors, particularly in the communications market.

Even ASICs present a bleak outlook and are likely going the way of gate arrays! The graph here shows the declining ASIC market share.
The increasing development costs and reduced R&D investments by OEMs has been leading to accelerated erosion of ASIC market share going forward. In fact, the long-awaited tipping point where FPGAs replace gate arrays is upon us.

ASSP vendor challenges
Looking at ASSP vendors, those vendor in tier 1 face challenges such as business model viability and poor profitability. High risk environment leads to poor customer loyalty. The large capital outlay on fabbed is moving on to fablite and fabless. Next, market and customer consolidation means fewer deals for such vendors. Chase of >1M units means few applications and customers.

What about the tier 2 ASSP vendors challenge? They have been forced into very high volumes and compete poorly against the tier 1 vendors. Hence, profitability and business models are under severe pressure. It is to be noted that out of the 115-odd companies followed by the GSA (Global Semiconductor Alliance), 29 have market caps less than their cash.

As for the tier 3 ASSPs and startups challenge, the Round-A VC funding has dried up! Incidentally, the round-A funding (dollar amount) declined 82 percent from 2000 and 2007. Through Q308, only two chip companies received round-A funding, totaling $12 million.

Programmables next business disruption
Looking at the logic IC landscape, programmables are emerging as the next business disruption. FPGAs are no longer seen as a yearly cost burden prior to ASIC release, but more as a solution that could live in products and platforms over time.

The tipping point should happen in 2009, and programmables should reach a plateau of productivity by 2016!

Where Xilinx fits in!
Today, Xilinx sees growth opportunity ahead, and it is more of a pragmatic reality now! The company understands that new attributes are required to meet the challenges of the future. It lists three attributes to bring about this change:

* Transformation: Market led, semiconductor leader.
* Ushering in the era of targeted design platforms.
* World class, thriving third-party ecosystem.

Transformation is already underway at Xilinx, which is now becoming a market led, semiconductor business leader.

It is ushering in the era of targeted design platforms, which is enabling innovation. A view at the ASIC/ASSP class applications reveals that the positioning has become more market focused. The architecture is more toward market tuned platforms. Xilinx also focuses on low power leadership. Its design methodology has now become open, scalable and hierarchical.

Targeted design platforms also enable customers to do more, and faster, and focus on their differentiation! Xilinx also boasts a world class and thriving third-party ecosystem. The software and IP is scalable, standardized, extensible and collaborative.

Xilinx is striving to accelerate the programmable experience by giving what customers need, and when they need it! Its Virtex and Spartan silicon form the programmable foundation. It offers base targeted design platforms -- devices, software, IP, boards, etc. It also offers domain specific platforms, along with domain specific IP and tools, as well as market specific platforms, which are inclusive of market specific reference designs and IP.

According to Dhir, the company is offering innovative technology to address diverse market requirements and to drive programmable logic beyond the tipping point!

FPGA vs. ASIC and FPGA trends

This semicon blog is a continuation of the recent discussion I had with Vincent Ratford, Senior Vice President, Solutions Development Group, Xilinx.

FPGAs vs. ASICs
Traditionally, there has always been a classic debate: FPGAs vs. ASICs! To find out more on the current status of this ever going discussion, I asked Ratford for his thoughts on this topic.

He said: "To answer this you have to take a long term view and look forward five years to what a 22nm device might look like and the cost to develop it. ASIC starts have declined over the last five years and continue to decline with ASSPs taking their place. For ASSPs to continue, they have to amortize the development cost across multiple customers, but with $50M development costs climbing to $100M, the number of applications that can support this is shrinking.

"FPGAs now look like SoCs with embedded processors, signal processing, multi-gigabit transceivers and a broad portfolio of IPs available from Xilinx or third parties. With shorter design cycles and increasing need to differentiate or die, we believe the world is increasingly turning to programmable devices.

"The investments we [Xilinx] are making in IP and software to enable more complex systems to be designed will carry our silicon platform forward and enable growth. Our challenges, going forward, are reducing power, providing more capability at a lower cost and simplifying the programming. As we make progress on all these fronts, we will take share from the ASIC/ASSP providers."

Global FPGA industry trends
Given the current semiconductor scenario, there is a need to estimate the global FPGA industry. According to iSuppli, the programmable logic market was $3.6 billion in CY2007. Xilinx revenues were $1.841 billion.

Given the wobble in the current global semicon scenario, where is the FPGA industry headed? Ratford said that Xilinx is forecasting 5-9 percent growth in FY09, which started in April 2008.

He added: "Our most recent quarter ending June was a record quarter for the company at $488 million, with 4 percent sequential growth. Our customers' design cycles are 12-18 months, so that tends to delay any weakness. However, design activity has been and still is strong. Our customers are highly diversified with over 20,000 across all the vertical markets. We see strong growth in ISM, automotive, aerospace and defense, and slow growth in telecommunications, which is our largest market at ~46 percent of sales."

According to him, wireless telecom, which constitutes about 40 percent of Xilinx's telecom revenue, is starting to go through a round of infrastructure buildouts with LTE and TD-SCDMA. This occurs about every five years.

"As these start to deploy, we expect to see some growth beyond what we are currently seeing. Finally, customers do a lot of prototyping with our platforms. We see no significant slowdown at this time," he noted.

Taking on Altera
Altera recently released the Stratix IV FPGA and HardCopy ASICs. It would be interesting to find out whether Xilinx has released anything that is close to or better than the Altera Stratix IV FPGA or the HardCopy ASIC.

Xilinx's Ratford said: "Our Virtex-5 products on 65nm have been shipping for 18 months, growing quickly and gaining market share vs. Stratix-3, which is also on 65nm. Since Altera has had difficulty executing on 65nm as far as Stratix III is concerned, they've had to jump to 45/40nm and recently pre-announced Stratix IV. Altera is saying they will ship first samples by December, however it takes quite some time to ramp to volume on a node and to put in place all the software and IP required.

"Our 45/40nm design has been underway for some time and we'll be in the market with a complete solution at the same time as Altera. What matters is when you ramp to production and when you have critical mass of IP so customers can start designs. We have a much larger IP portolio. Customer design activity on high-end FPGA will remain on 65nm devices for sometime to come. We estimate that Xilinx has about a 97 percent market-share in the high-end with our Virtex-5 family.

Alternative to HardCopy
Apparently, Xilinx also has an alternative to Altera's HardCopy. Ratford pointed to Xilinx's EasyPath, which provides similar cost reduction path for customers.

"Our approach doesn't require design compromises like that of HardCopy. Altera's most recent quarter showed HardCopy revenue down 2 percent to about $10M/quarter. It's insignificant!"

The last part of this discussion continues later this week! Watch this space, dear readers.

India is Xilinx's most active region for design activity!

Xilinx has been a global leader in programmable logic solutions with over 51 percent market share during 2007, according to iSuppli. PLDs represent an exciting growth potential in the chip market thanks to their flexible nature and ability to change functionality even after being manufactured.

I caught up with Vincent Ratford, Senior Vice President, Solutions Development Group, Xilinx, to find out more about the company's role in India. Firstly, Xilinx clearly sees India and Asia/Pac as a high growth area for its business.

Ratford said: "India itself has a lot of design activity with many of our customers working with design services and IP companies there. For that reason, we have invested in a large engineering team (125 people and grew last year at 60 percent) working on IP, software, system applications and IC design. These teams augment global development teams around the world with some teams having product responsibility."

As a company, Xilinx tracks design activity and production, and India is its most active region for design activity. It is also investing a lot in university programs.

He added: "We have significant market share in India vs. the other FPGA vendors. We expect this to continue. We are investing heavily in our Xilinx University Program providing tool, board, training for professors and setting up FPGA, embedded and DSP curriculums. We have a strong technical team supporting customers locally either directly or alongside of our distribution partners."

So how does Xilinx view the strength of the Indian embedded design segment? Ratford referred to EETimes, which conducts a survey annually on embedded processing. The most recent data showed only about 1/3 of the embedded users using FPGAs, but over 50 percent of them were considering.

He said: "I think we have just scratched the surface on our embedded opportunity. We have over 10k licensed embedded users worldwide, with the smallest percentage in Asia/Pac, but it's growing rapidly.

"We think there is a lot of unlicensed, and therefore, untracked useage. Going forward, we will be able to track adoption more closely. We are now starting to track useage with our WebTalk tool and have found that about half of the designs using our latest 10.1 release have processors on them. Finally, when we conduct seminars and workshops worldwide, our embedded sessions are the most heavily attended."

On the role that Xilinx would be playing in India, he said: "Today, we have a strong offering in soft and hard processors for our Virtex and Spartan series FPGAs. We are investing in training and providing development kits to expand the number of embedded developers who can support our platforms.

"We have been developing embedded peripherals, device drivers and are now starting to develop embedded tools there. We expect to expand this. So it's market development, product development and enabling our ecosystem partners to build on top of our platforms. We are investing in India faster than any other region and plan to leverage our development team there."

Think AND not OR; Altera first @ 40nm FPGAs

Altera has announced two new product lines -- the Stratix IV FPGAs, which feature up to 680K logic elements, as well as the HardCopy IV ASICs, which has Gigabit transceivers embedded within the PLCs and allow seamless FPGA prototyping to hard core ASIC production.

Altera has also introduced the Quartus II software v8.0, which delivers unprecedented performance and productivity for FPGAs. It allows customers to assign power constraints on designs.

This is a global launch, and I feel proud to be associated with it. I am probably among the earliest to break this news to the world!

"All of these have been made possible due to Altera's relationship with TSMC," according to Gangatharan Gopal, country manager, India, Altera Semiconductor India Pvt. Ltd.

Altera's 40nm devices are targeted at high-end applications such as wireless and wireline communications, military, broadcasting and ASIC prototyping.

The Statix IV FPGAs feature 680K logic elements, up to 22.4Mbits internal RAM, up to 48 transceiver blocks operating at up to 8.5Gbps, core performance of 350MHz, and hard IP for PCI Express Gen 1 and Gen 2.

The Stratix IV FPGAs are available in two majpr product groups -- the GX devices or Gigabit Ethernet devices, which have up to 530K logic elements, and the E devices or enhanced Stratix IV, which support more memory per logic element. There are a total of eight devices per family.

The HardCopy ASICs IV feature seamless prototyping, so that customers can have the same RTL, same IP set and one tool, come with transceivers -- similar transceiver block as the Stratix IV, offer lowest risk and lowest total cost access to deep sub-micron ASIC benefits, and provde 50x low power than companion FPGAs.

The HardCopy IV features 13.3 million gates. Gopal said: "Altera has surpassed the average industry ASIC density. We are now offering 13.3 million gates with HardCopy IV. With this, we can now address 80 percent of the market requirements."

The HardCopy IV also comes in GX and E versions. Each version has six devices, supporting more memories and transceiver blocks.

Higher densities require higher levels of productivity
Altera's Quartus II software v8.0 is specifically addressing this market need. It is said to be leading in productivity for high-end FPGAs and HardCopy ASICs. Features include TimeQuest -- for timing analysis, Compilation Speed -- via incremental compilation, PowerPlay technology -- which allows power management; and SOPC Builder -- which facilitates system-level design.

Altera is addressing the issue of compile times at three fronts -- algorithms, multiprocessor support and incremental compile support. The Quartus II v8.0 is said to deliver 20 percent average annual compile time improvement.