MOUNTAIN VIEW, USA: Synopsys Inc. today announced that the Common Platform technology alliance, a unique technology collaboration between IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, has qualified IC Validator for 32-nanometer (nm) process design rule checking on Common Platform technology.
Synopsys and the Common Platform companies are continuing with the collaboration to complete the qualification of IC Validator at 28nm on Common Platform technology. IC Validator, the newest addition to the Galaxy Implementation Platform, is a full signoff DRC/LVS solution.
In addition, the IC Validator has been uniquely architected as an ideal add-on to IC Compiler for in-design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
This qualification enables Common Platform customers to deploy IC Validator into production use at 32nm and see benefits from the productivity advantages of in-design physical verification in conjunction with the IC Compiler place and route solution.
"We believe that in-design physical verification is essential to significantly reduce physical verification turnaround time given the complexities at emerging nodes," said Henry Law, vice president, design services division for Chartered, on behalf of the Common Platform alliance companies.
"Architected for 45nm and below process nodes, IC Validator offers a highly flexible programming language that makes runset creation at these complex nodes easy and concise. Our qualification of IC Validator confirmed its signoff accuracy and productivity benefits of in-design physical verification. Given the observed benefits, we are committed to qualifying IC Validator for the Common Platform 28nm process node."
Prevalent approaches to physical design and verification can be described as "implement-then-verify" and result in multiple iterations between design and signoff. In-design physical verification accelerates design closure by enabling sign-off quality rule checking and fixing during the design process, avoiding late stage surprises that can jeopardize project schedules.
Other benefits include incremental processing, automatic error detection and fixing, near-linear scalability across multiple CPU cores and the elimination of expensive stream-outs and stream-ins. IC Validator also offers significant automation and innovative features such as DRC error classification or DRC waiver, multi-user collaboration, customized reporting and on-the-fly error reporting that can further improve physical verification turnaround time.
While in-design physical verification is facilitated by seamless integration with IC Compiler, IC Validator's foundry-endorsed, signoff-accurate engine is its core strength. Powered by its hybrid data and command-processing engine, IC Validator is a full signoff DRC/LVS tool offering the high accuracy necessary for leading-edge process nodes, excellent scalability for efficient utilization of available hardware and high programmability for easier runset development.
For runset writers and CAD managers, IC Validator offers a flexible programming language that can cut runset size from 2 to 10x, lowering the cost of setting up, maintaining and modifying the physical verification environment.
"Common Platform technology companies have always been at the forefront in defining high-productivity flows for advanced processes," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This qualification marks an important milestone in supporting leading-edge technology from the Common Platform alliance and will bring IC Validator's unique value proposition to our mutual customers and partners. We look forward to our continued collaboration towards the 28-nm qualification."
Showing posts with label Chartered Semiconductor. Show all posts
Showing posts with label Chartered Semiconductor. Show all posts
Wednesday, 30 September 2009
Tuesday, 8 September 2009
A*STAR, EDB launch 3D TSV Consortium
SINGAPORE: The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR), launched a 3-Dimensional (3D) Through-Silicon Via (TSV) consortium to boost next generation 300mm wafer manufacturing capability for Singapore semiconductor industry to meet technology and product needs.
The consortium is a national initiative and supported by the Singapore Economic Development Board (EDB) and A*STAR. IME is teaming up with A*STAR’s Institute of High Performance Computing (IHPC) and Nanyang Technological University (NTU) in the consortium, which consists of two phases with a duration of 18 months for each phase.
IME is leading phase 1 of the consortium with participating companies that include Chartered Semiconductor Manufacturing Ltd, STATS ChipPAC Ltd and United Test and Assembly Center Ltd. The consortium will also leverage on strategic materials and equipment suppliers for support in its endeavours.
For over 40 years, the semiconductor industry has relied on Moore’s Law to steadily increase the number of transistors by shrinking its geometry thus allowing more functions to be designed in an IC chip. The demand for miniaturisation and greater functionality in electronic devices has driven transistor geometries so small, we are soon reaching the scaling limit for semiconductor process technology.
To put in perspective, the size of the state-of-the-art transistor is in the order of 30 nanometres which is about 3,000 times smaller than the diameter of a strand of human hair. An approach to circumvent the continued shrinking of planar ICs and scaling limitation by stacking of IC chips or packages vertically is known as 3D IC integration.
One of the enabling technologies for 3D IC integration is Through-Silicon Via (TSV). TSV is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction.
The goal of phase 1 is to establish TSV design and processes for 200mm and 300mm TSV wafers 3D IC assembly, and train a pool of skilled personnel in the semiconductor supply chain companies to support manufacturing of new products with 3D TSVs. Phase 2 will demonstrate the integration of fully functional mobile devices with TSV on a 300mm wafer process line.
Prof. Dim-Lee Kwong, Executive Director of IME, said: “The launch of this consortium is timely as the semiconductor industry is grappling to find solutions to extend the limit of transistor scaling beyond Moore’s Law. TSV opens up new possibilities to add complex and multi-functional features to electronic devices by allowing ICs or packages to be stacked vertically.
“Over the last few years, IME has established deep competencies and process capabilities for TSV carriers. What is unique in this consortium is that we are able to gather key companies across the Singapore semiconductor supply chain to establish cost-effective TSV process integration and manufacturing capability on 300mm wafers to help accelerate the industry adoption of 3D ICs with TSV.”
Dr. Raj Thampuran, Executive Director of IHPC, added, “IHPC is delighted to be a part of this consortium. Modelling and simulation capabilities will certainly help to predict and optimise the performance in the complex design of the TSV carriers.”
According to Prof. Kam Chan Hin, Chair of School of Electrical and Electronic Engineering at NTU, “This consortium has also provided Nanyang Technological University a platform and new opportunity to work more closely with our partners to bring academic research to the industry.”
Commenting on the value creation of R&D to industry, Prof. Chong Tow Chong, Executive Director of A*STAR’s Science and Engineering Research Council, added: “One of A*STAR’s objectives is to promote R&D in fields that add value and grow the Singapore’s manufacturing industry. This consortium exemplifies how A*STAR research institutes work with companies and institutes of higher learning to identify and develop next-generation capabilities and technology to enhance the competitiveness of the semiconductor industry in Singapore.”
Damian Chan, Director of Electronics Cluster at Singapore Economic Development Board, said: “Our vibrant semiconductor ecosystem consisting of IC design, wafer fabrication, advanced assembly and test, and supported by a strong base of suppliers offers a “Plug and Play” environment. The concentrated ecosystem allows semiconductor companies to easily find their business partners while enjoying access to the international market.”
He added that: “R&D is the key to strong growth in the future. This industry-public research collaboration is a unique opportunity for global players such as Chartered, STATS ChipPAC and UTAC to leverage on each other’s unique expertise and co-develop this emerging technology to address the needs of the industry.”
Here are comments from some of the consortium members on the impact of the 3D TSV consortium in addressing the needs of the Singapore semiconductor industry supply chain:
"Chartered understands that our customers need technology and solutions that address their requirements in performance, cost and scaling. The 3D TSV Consortium allows Chartered to focus on our core competency in TSV silicon integration while leveraging the expertise of our partners in material research, design, bonding, packaging and testing. The result is a proven 3D TSV infrastructure from design to tested package," said Dr. Liang-Choo “LC” Hsia, Senior Vice President of Technology Development at Chartered.
"In joining the consortium, Chartered will be part of the significant 3D TSV Infrastructure value chain in Singapore."
“We believe the depth of expertise at IME and the consortium members, combined with the knowledge we have on driving integration technology and flexibility at the silicon level will provide important momentum in developing 3D TSV technology into high volume IC packaging solutions. Our involvement with the 3D TSV consortium will complement the research and development activities we have been working on in advanced wafer integration technology,” said Il Kwon Shim, Vice President, Technology Innovation of STATS ChipPAC Ltd.
“The new capabilities acquired from this strategic consortium will help UTAC increase our service offerings to our customers. The innovative capabilities and technologies will provide greater efficiencies in our delivery of customer focused solutions. UTAC believes in partnering our customers to provide leading edge semiconductor solutions through teamwork and enterprising spirit. We are committed to meet our customer's expectations by providing quality products and services through the creative involvement of our employees and a culture of continuous improvement to offer higher value added services to our customers,” said Dr. Anthony Sun, Group Vice President of R&D of UTAC.
The consortium is a national initiative and supported by the Singapore Economic Development Board (EDB) and A*STAR. IME is teaming up with A*STAR’s Institute of High Performance Computing (IHPC) and Nanyang Technological University (NTU) in the consortium, which consists of two phases with a duration of 18 months for each phase.
IME is leading phase 1 of the consortium with participating companies that include Chartered Semiconductor Manufacturing Ltd, STATS ChipPAC Ltd and United Test and Assembly Center Ltd. The consortium will also leverage on strategic materials and equipment suppliers for support in its endeavours.
For over 40 years, the semiconductor industry has relied on Moore’s Law to steadily increase the number of transistors by shrinking its geometry thus allowing more functions to be designed in an IC chip. The demand for miniaturisation and greater functionality in electronic devices has driven transistor geometries so small, we are soon reaching the scaling limit for semiconductor process technology.
To put in perspective, the size of the state-of-the-art transistor is in the order of 30 nanometres which is about 3,000 times smaller than the diameter of a strand of human hair. An approach to circumvent the continued shrinking of planar ICs and scaling limitation by stacking of IC chips or packages vertically is known as 3D IC integration.
One of the enabling technologies for 3D IC integration is Through-Silicon Via (TSV). TSV is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction.
The goal of phase 1 is to establish TSV design and processes for 200mm and 300mm TSV wafers 3D IC assembly, and train a pool of skilled personnel in the semiconductor supply chain companies to support manufacturing of new products with 3D TSVs. Phase 2 will demonstrate the integration of fully functional mobile devices with TSV on a 300mm wafer process line.
Prof. Dim-Lee Kwong, Executive Director of IME, said: “The launch of this consortium is timely as the semiconductor industry is grappling to find solutions to extend the limit of transistor scaling beyond Moore’s Law. TSV opens up new possibilities to add complex and multi-functional features to electronic devices by allowing ICs or packages to be stacked vertically.
“Over the last few years, IME has established deep competencies and process capabilities for TSV carriers. What is unique in this consortium is that we are able to gather key companies across the Singapore semiconductor supply chain to establish cost-effective TSV process integration and manufacturing capability on 300mm wafers to help accelerate the industry adoption of 3D ICs with TSV.”
Dr. Raj Thampuran, Executive Director of IHPC, added, “IHPC is delighted to be a part of this consortium. Modelling and simulation capabilities will certainly help to predict and optimise the performance in the complex design of the TSV carriers.”
According to Prof. Kam Chan Hin, Chair of School of Electrical and Electronic Engineering at NTU, “This consortium has also provided Nanyang Technological University a platform and new opportunity to work more closely with our partners to bring academic research to the industry.”
Commenting on the value creation of R&D to industry, Prof. Chong Tow Chong, Executive Director of A*STAR’s Science and Engineering Research Council, added: “One of A*STAR’s objectives is to promote R&D in fields that add value and grow the Singapore’s manufacturing industry. This consortium exemplifies how A*STAR research institutes work with companies and institutes of higher learning to identify and develop next-generation capabilities and technology to enhance the competitiveness of the semiconductor industry in Singapore.”
Damian Chan, Director of Electronics Cluster at Singapore Economic Development Board, said: “Our vibrant semiconductor ecosystem consisting of IC design, wafer fabrication, advanced assembly and test, and supported by a strong base of suppliers offers a “Plug and Play” environment. The concentrated ecosystem allows semiconductor companies to easily find their business partners while enjoying access to the international market.”
He added that: “R&D is the key to strong growth in the future. This industry-public research collaboration is a unique opportunity for global players such as Chartered, STATS ChipPAC and UTAC to leverage on each other’s unique expertise and co-develop this emerging technology to address the needs of the industry.”
Here are comments from some of the consortium members on the impact of the 3D TSV consortium in addressing the needs of the Singapore semiconductor industry supply chain:
"Chartered understands that our customers need technology and solutions that address their requirements in performance, cost and scaling. The 3D TSV Consortium allows Chartered to focus on our core competency in TSV silicon integration while leveraging the expertise of our partners in material research, design, bonding, packaging and testing. The result is a proven 3D TSV infrastructure from design to tested package," said Dr. Liang-Choo “LC” Hsia, Senior Vice President of Technology Development at Chartered.
"In joining the consortium, Chartered will be part of the significant 3D TSV Infrastructure value chain in Singapore."
“We believe the depth of expertise at IME and the consortium members, combined with the knowledge we have on driving integration technology and flexibility at the silicon level will provide important momentum in developing 3D TSV technology into high volume IC packaging solutions. Our involvement with the 3D TSV consortium will complement the research and development activities we have been working on in advanced wafer integration technology,” said Il Kwon Shim, Vice President, Technology Innovation of STATS ChipPAC Ltd.
“The new capabilities acquired from this strategic consortium will help UTAC increase our service offerings to our customers. The innovative capabilities and technologies will provide greater efficiencies in our delivery of customer focused solutions. UTAC believes in partnering our customers to provide leading edge semiconductor solutions through teamwork and enterprising spirit. We are committed to meet our customer's expectations by providing quality products and services through the creative involvement of our employees and a culture of continuous improvement to offer higher value added services to our customers,” said Dr. Anthony Sun, Group Vice President of R&D of UTAC.
Consolidation changing the foundry landscape
USA: Change is on the horizon. Advanced Technology Investment Company LLC (ATIC) and Chartered Semiconductor Manufacturing (Chartered) have entered into a definitive agreement whereby ATIC will acquire Chartered. What does this mean?
Semico does not think that TSMC will be ‘dethroned’ as the leading foundry but it does mean that the number two spot is definitely up for grabs. Semico’s data indicates that by 2011, the combined GlobalFoundries/Chartered company will out pace UMC in terms of advanced capacity available for production.
Source: Semico Research
Semico does not think that TSMC will be ‘dethroned’ as the leading foundry but it does mean that the number two spot is definitely up for grabs. Semico’s data indicates that by 2011, the combined GlobalFoundries/Chartered company will out pace UMC in terms of advanced capacity available for production.
Source: Semico Research
Sunday, 6 September 2009
ATIC makes bid to acquire Chartered Semiconductor
SINGAPORE: Advanced Technology Investment Co. LLC (ATIC) of Abu Dhabi and Chartered Semiconductor Manufacturing (Chartered) of Singapore announced a definitive agreement whereby ATIC would acquire Chartered, one of the world’s top dedicated semiconductor foundries.
Offer details
The proposed acquisition will be effected by way of a scheme of arrangement under section 210 of the Companies Act of Singapore, subject to the approval of Chartered shareholders and the sanction of the High Court of Singapore. The transaction is expected to close during the fourth quarter of 2009.
Completion of the transaction will be subject to customary conditions, such as regulatory and shareholder approvals. Details can be found in the joint scheme announcement that has been filed with the Singapore Exchange Securities Trading Limited (SGX), as well as in the scheme document to be sent to Chartered shareholders.
Under this scheme of arrangement, each Chartered ordinary share will be acquired by ATIC for a cash consideration of S$2.68 per share. The transaction represents an equity value of approximately S$2.5 billion (US$1.8 billion) and a total value of approximately S$5.6 billion (US$3.9 billion), including debt and convertible redeemable preference shares of approximately S$3.1 billion (US$2.2 billion) as of June 30, 2009.
The price represents a premium of 14.2 percent to its 30 trading-day volume weighted average price, 26.8 percent to its 90 trading-day volume weighted average price and 44.2 percent to its 6-month volume weighted average price on the SGX. The estimated amount of consideration for each American Depositary Share ("ADSs") is US$18.641. The actual amount per ADS that ADS holders will receive will depend on the applicable prevailing exchange rate, less the amount of applicable ADS depositary's fees, taxes and expenses.
ATIC is a technology investment company wholly owned by the government of Abu Dhabi. This acquisition is its second major investment in the semiconductor industry and follows the company’s March 2009 creation of GLOBALFOUNDRIES, a US-headquartered, leading-edge semiconductor manufacturing company and a joint venture with AMD.
The acquisition of Chartered will be made through ATIC International Investment Co. LLC, a subsidiary of ATIC. Once the transaction is completed, ATIC will be the sole owner of Chartered.
The transaction will allow ATIC to build on the complementary platforms of Chartered and GLOBALFOUNDRIES, with Chartered’s customer relationships and capabilities in both 8-inch and 12-inch fabrication, and GLOBALFOUNDRIES’ advanced technology expertise, capacity profile and global footprint.
“We believe that by having access to ATIC’s long-term capital and related assets, Chartered has an opportunity to bring its skills, capabilities and leadership to the next level,” said Waleed Al Mokarrab, Chairman of ATIC. “By acquiring Chartered, ATIC is expanding its investments in the semiconductor industry which currently consist of a GLOBALFOUNDRIES leading facility in Dresden, Germany and a new, state-of-the-art facility under construction in upstate New York.”
Pending appropriate board approvals, Doug Grose, chief executive officer of GLOBALFOUNDRIES, would serve as CEO of the combined operations, with Chia Song Hwee, CEO of Chartered, serving as chief operating officer. Chia will also spearhead the integration effort.
“Chartered’s board of directors recognizes the efforts of the management team and employees on the considerable progress they have made,” said Jim Norling, chairman of the board of directors at Chartered.
“Given the importance of scale and the need for substantial, continued capital investment, and having carefully assessed all strategic options available to Chartered, we believe this transaction provides Chartered shareholders the opportunity to realize their investment. In addition, it enables Chartered to accelerate its goal of becoming a leading player in the semiconductor industry.
“We have today appointed Deutsche Bank AG, Singapore Branch as an independent financial advisor to advise shareholders on the fairness of the offer, and we will submit the proposal for a shareholder vote.”
Morgan Stanley Asia (Singapore) Pte. and Citigroup Global Markets Singapore Pte. Ltd. serve as joint financial advisors to Chartered, and each provided a fairness opinion to the board of directors of Chartered in connection with the transaction.
Temasek Holdings, which currently owns approximately 62 percent of Chartered’s shares, also fully supports the acquisition and has signed an irrevocable undertaking to vote in support of the transaction.
“Chartered and GLOBALFOUNDRIES will be able to draw on each other’s strengths to enable the next generation of semiconductor innovation, utilizing the value of both companies and the intellectual capital of thousands of skilled employees,” said Ibrahim Ajami, CEO of ATIC. “Chartered and GLOBALFOUNDRIES are well positioned to meet the growing chip demand to come from billions of new mobile phones, cars, televisions, computers and other devices.”
Offer details
The proposed acquisition will be effected by way of a scheme of arrangement under section 210 of the Companies Act of Singapore, subject to the approval of Chartered shareholders and the sanction of the High Court of Singapore. The transaction is expected to close during the fourth quarter of 2009.
Completion of the transaction will be subject to customary conditions, such as regulatory and shareholder approvals. Details can be found in the joint scheme announcement that has been filed with the Singapore Exchange Securities Trading Limited (SGX), as well as in the scheme document to be sent to Chartered shareholders.
Under this scheme of arrangement, each Chartered ordinary share will be acquired by ATIC for a cash consideration of S$2.68 per share. The transaction represents an equity value of approximately S$2.5 billion (US$1.8 billion) and a total value of approximately S$5.6 billion (US$3.9 billion), including debt and convertible redeemable preference shares of approximately S$3.1 billion (US$2.2 billion) as of June 30, 2009.
The price represents a premium of 14.2 percent to its 30 trading-day volume weighted average price, 26.8 percent to its 90 trading-day volume weighted average price and 44.2 percent to its 6-month volume weighted average price on the SGX. The estimated amount of consideration for each American Depositary Share ("ADSs") is US$18.641. The actual amount per ADS that ADS holders will receive will depend on the applicable prevailing exchange rate, less the amount of applicable ADS depositary's fees, taxes and expenses.
ATIC is a technology investment company wholly owned by the government of Abu Dhabi. This acquisition is its second major investment in the semiconductor industry and follows the company’s March 2009 creation of GLOBALFOUNDRIES, a US-headquartered, leading-edge semiconductor manufacturing company and a joint venture with AMD.
The acquisition of Chartered will be made through ATIC International Investment Co. LLC, a subsidiary of ATIC. Once the transaction is completed, ATIC will be the sole owner of Chartered.
The transaction will allow ATIC to build on the complementary platforms of Chartered and GLOBALFOUNDRIES, with Chartered’s customer relationships and capabilities in both 8-inch and 12-inch fabrication, and GLOBALFOUNDRIES’ advanced technology expertise, capacity profile and global footprint.
“We believe that by having access to ATIC’s long-term capital and related assets, Chartered has an opportunity to bring its skills, capabilities and leadership to the next level,” said Waleed Al Mokarrab, Chairman of ATIC. “By acquiring Chartered, ATIC is expanding its investments in the semiconductor industry which currently consist of a GLOBALFOUNDRIES leading facility in Dresden, Germany and a new, state-of-the-art facility under construction in upstate New York.”
Pending appropriate board approvals, Doug Grose, chief executive officer of GLOBALFOUNDRIES, would serve as CEO of the combined operations, with Chia Song Hwee, CEO of Chartered, serving as chief operating officer. Chia will also spearhead the integration effort.
“Chartered’s board of directors recognizes the efforts of the management team and employees on the considerable progress they have made,” said Jim Norling, chairman of the board of directors at Chartered.
“Given the importance of scale and the need for substantial, continued capital investment, and having carefully assessed all strategic options available to Chartered, we believe this transaction provides Chartered shareholders the opportunity to realize their investment. In addition, it enables Chartered to accelerate its goal of becoming a leading player in the semiconductor industry.
“We have today appointed Deutsche Bank AG, Singapore Branch as an independent financial advisor to advise shareholders on the fairness of the offer, and we will submit the proposal for a shareholder vote.”
Morgan Stanley Asia (Singapore) Pte. and Citigroup Global Markets Singapore Pte. Ltd. serve as joint financial advisors to Chartered, and each provided a fairness opinion to the board of directors of Chartered in connection with the transaction.
Temasek Holdings, which currently owns approximately 62 percent of Chartered’s shares, also fully supports the acquisition and has signed an irrevocable undertaking to vote in support of the transaction.
“Chartered and GLOBALFOUNDRIES will be able to draw on each other’s strengths to enable the next generation of semiconductor innovation, utilizing the value of both companies and the intellectual capital of thousands of skilled employees,” said Ibrahim Ajami, CEO of ATIC. “Chartered and GLOBALFOUNDRIES are well positioned to meet the growing chip demand to come from billions of new mobile phones, cars, televisions, computers and other devices.”
Monday, 3 August 2009
Rockchip allies with Synopsys, Chartered to achieve first-pass silicon success
FUZHOU, CHINA, MOUNTAIN VIEW, USA, & SINGAPORE: Fuzhou Rockchip Electronics Co. Ltd., Synopsys, Inc. and Chartered Semiconductor Manufacturing Ltd. announced that Rockchip has achieved first-time silicon success on its next-generation multimedia system-on-a-chip (SoC), using a combination of Synopsys' tools, intellectual property (IP) and services with Chartered's 65nm manufacturing technology.
The RK 28 multimedia SoC, Rockchip's first mass-production 65nm chip designed in China and targeted primarily for the China market, is an application processor for mobile handheld devices.
The RK28 chip was designed with Synopsys' full RTL-to-GDSII flow using best-in-class technology from the Galaxy Implementation and Discovery Verification Platforms, as well as DesignWare IP, and implemented in Chartered's advanced low-power (65nm LP) process.
"The mobile applications served by our customers require chips that can meet stringent low-power specifications without compromising performance, and our multimedia RK28 SoC delivers on both fronts," said Feng Chen, chief marketing officer of Rockchip.
"Our EDA and manufacturing partners played key roles in the success of our program. Our ability to reach design closure within our market window then rapidly move from tapeout to production silicon validates the choices we made with Synopsys and Chartered."
Since the 65nm RK28 represented Rockchip's first design at a new technology node, production-proven technology and knowledge sharing among the parties were essential to project success.
The design took advantage of Synopsys' IC Compiler with Zroute technology to exceed its 500MHz performance target, while employing advanced low-power design techniques such as multi-voltage and power gating to reduce power consumption.
The production-proven VMM verification methodology and VCS functional verification solution were used to verify Rockchip's design. The RK28 chip also integrates silicon-proven Synopsys DesignWare IP, including USB 2.0 PHY, USB HS OTG Controller and SD/MMC Host Controller.
Design consultants from Synopsys Professional Services worked closely with Rockchip's engineers throughout the project, merging critical skills and expertise to mitigate project risks and address schedule pressures. The implementation of the design in Chartered's 65nm LP process enabled the chip to achieve target power, performance and area goals with first silicon, and quickly ramp to production volume.
"At Chartered, we understand our customers need technology and solutions with low risk and high yield to speed time to market, and we are pleased to see our collaboration with Rockchip and Synopsys achieve first-pass silicon success," said Dr. Liang-Choo "LC" Hsia, senior vice president of technology development at Chartered.
"The Rockchip-Synopsys-Chartered collaboration demonstrates how a strong foundation can support companies on the leading edge of design, especially those in the consumer entertainment and mobile applications."
"Rockchip joins a growing list of innovative chip developers that are taking advantage of Synopsys' broad portfolio of tools, IP and services to accomplish their aggressive design goals with efficiency," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our collaboration with Rockchip and Chartered demonstrates our commitment to serve customers in China and the rest of the world with solutions that accelerate tapeout and enhance manufacturability."
The RK 28 multimedia SoC, Rockchip's first mass-production 65nm chip designed in China and targeted primarily for the China market, is an application processor for mobile handheld devices.
The RK28 chip was designed with Synopsys' full RTL-to-GDSII flow using best-in-class technology from the Galaxy Implementation and Discovery Verification Platforms, as well as DesignWare IP, and implemented in Chartered's advanced low-power (65nm LP) process.
"The mobile applications served by our customers require chips that can meet stringent low-power specifications without compromising performance, and our multimedia RK28 SoC delivers on both fronts," said Feng Chen, chief marketing officer of Rockchip.
"Our EDA and manufacturing partners played key roles in the success of our program. Our ability to reach design closure within our market window then rapidly move from tapeout to production silicon validates the choices we made with Synopsys and Chartered."
Since the 65nm RK28 represented Rockchip's first design at a new technology node, production-proven technology and knowledge sharing among the parties were essential to project success.
The design took advantage of Synopsys' IC Compiler with Zroute technology to exceed its 500MHz performance target, while employing advanced low-power design techniques such as multi-voltage and power gating to reduce power consumption.
The production-proven VMM verification methodology and VCS functional verification solution were used to verify Rockchip's design. The RK28 chip also integrates silicon-proven Synopsys DesignWare IP, including USB 2.0 PHY, USB HS OTG Controller and SD/MMC Host Controller.
Design consultants from Synopsys Professional Services worked closely with Rockchip's engineers throughout the project, merging critical skills and expertise to mitigate project risks and address schedule pressures. The implementation of the design in Chartered's 65nm LP process enabled the chip to achieve target power, performance and area goals with first silicon, and quickly ramp to production volume.
"At Chartered, we understand our customers need technology and solutions with low risk and high yield to speed time to market, and we are pleased to see our collaboration with Rockchip and Synopsys achieve first-pass silicon success," said Dr. Liang-Choo "LC" Hsia, senior vice president of technology development at Chartered.
"The Rockchip-Synopsys-Chartered collaboration demonstrates how a strong foundation can support companies on the leading edge of design, especially those in the consumer entertainment and mobile applications."
"Rockchip joins a growing list of innovative chip developers that are taking advantage of Synopsys' broad portfolio of tools, IP and services to accomplish their aggressive design goals with efficiency," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our collaboration with Rockchip and Chartered demonstrates our commitment to serve customers in China and the rest of the world with solutions that accelerate tapeout and enhance manufacturability."
Thursday, 30 July 2009
More positive indicators for semicon equipment market
NEW TRIPOLI, USA: Expected announcements that capex was increasing are giving hope that the equipment downturn has bottomed out, according to the report “The Global Market for Equipment and Materials for IC Manufacturing,” recently published by The Information Network.
We noted in our TheStreet.com column on Tuesday that “Singapore-based foundry Chartered Semiconductor raised its 2009 capital budget forecast by a third on growing demand, and we expect similar positive activity coming from Taiwan-based foundries TSMC and UMC as they report this week.”
Well, Taiwan's United Microelectronics Corp. (UMC) reported on Wednesday that it was, in fact, raising its capex morning for CY09 from less than $400 million to $500 million. Taiwan Semiconductor Manufacturing Co (TSMC) also revised upward its 2009 capex budget to $2.3 billion. Previously, it estimated a capex of $1.9 billion for the year.
For UMC, revenue increased 108.8 percent quarter-over-quarter and wafer shipments increased 134 percent sequentially to 898 thousand in the second quarter, compared to 384 thousand 8-inch equivalent wafers shipped in the first quarter. The overall utilization rate for the quarter was 79 percent, compared to 30 percent in the previous quarter and 85 percent a year ago.
For TSMC, the world’s largest foundry, revenues for the second quarter were up 87.9 percent sequentially. TSMC recorded wafer shipments of 1.97 million 8-inch equivalent units in the second quarter, up 121 percent from 892,000 units in the first.
We stated in our TheStreet.com column last Thursday that the chip market recovery had begun, but tightened purse strings was keeping the semiconductor equipment market from exhibiting comparable up and down cycles characteristic of the semiconductor market.
We stated that “In January 1995, 11.4 percent of revenue generated by semiconductor manufacturers was spent on new processing equipment. Forward to May 2009 and only 3.8 percent of semiconductor revenue was spent on equipment.”
As shown in the chart below, up until 2001, the semiconductor and the semiconductor markets moved in tandem, exhibiting a peak and a valley every three years. After 2001, things changed –- the semiconductor market continued strong growth until late 2008 while the equipment market was essentially flat until mid-2008.
Source: The Information Network
For 2009, we forecast that the semiconductor equipment market will drop 46 percent. In contrast, we forecast the semiconductor market will drop 26 percent in 2009. Most importantly, growth in the equipment market will continue through 2012, increasing 20 percent in 2010 and 49 percent in 2011.
We noted in our TheStreet.com column on Tuesday that “Singapore-based foundry Chartered Semiconductor raised its 2009 capital budget forecast by a third on growing demand, and we expect similar positive activity coming from Taiwan-based foundries TSMC and UMC as they report this week.”
Well, Taiwan's United Microelectronics Corp. (UMC) reported on Wednesday that it was, in fact, raising its capex morning for CY09 from less than $400 million to $500 million. Taiwan Semiconductor Manufacturing Co (TSMC) also revised upward its 2009 capex budget to $2.3 billion. Previously, it estimated a capex of $1.9 billion for the year.
For UMC, revenue increased 108.8 percent quarter-over-quarter and wafer shipments increased 134 percent sequentially to 898 thousand in the second quarter, compared to 384 thousand 8-inch equivalent wafers shipped in the first quarter. The overall utilization rate for the quarter was 79 percent, compared to 30 percent in the previous quarter and 85 percent a year ago.
For TSMC, the world’s largest foundry, revenues for the second quarter were up 87.9 percent sequentially. TSMC recorded wafer shipments of 1.97 million 8-inch equivalent units in the second quarter, up 121 percent from 892,000 units in the first.
We stated in our TheStreet.com column last Thursday that the chip market recovery had begun, but tightened purse strings was keeping the semiconductor equipment market from exhibiting comparable up and down cycles characteristic of the semiconductor market.
We stated that “In January 1995, 11.4 percent of revenue generated by semiconductor manufacturers was spent on new processing equipment. Forward to May 2009 and only 3.8 percent of semiconductor revenue was spent on equipment.”
As shown in the chart below, up until 2001, the semiconductor and the semiconductor markets moved in tandem, exhibiting a peak and a valley every three years. After 2001, things changed –- the semiconductor market continued strong growth until late 2008 while the equipment market was essentially flat until mid-2008.
Source: The Information NetworkFor 2009, we forecast that the semiconductor equipment market will drop 46 percent. In contrast, we forecast the semiconductor market will drop 26 percent in 2009. Most importantly, growth in the equipment market will continue through 2012, increasing 20 percent in 2010 and 49 percent in 2011.
Monday, 27 July 2009
ARM, Chartered, IBM, Samsung and Synopsys to deliver vertically optimized solution for 32/28nm mobile SoC designs
SAN FRANCISCO, USA: In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor Manufacturing Ltd, IBM, Samsung Electronics Co. Ltd and Synopsys Inc. announced at the Design Automation Conference (DAC) an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices.
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
Monday, 13 July 2009
Chartered offers 65nm RF platform for single-chip wireless apps
SINGAPORE: Chartered Semiconductor Manufacturing, one of the world’s top dedicated foundries, today announced a robust 65nm RF platform specifically geared for developers of single-chip RF products.
The Chartered process offering, jointly developed with IBM, is based on Chartered’s enhanced 65nm low-power process (65nm LPe), and includes an IBM RF physical design kit (PDK) available from Chartered. This RF Platform comes with broad RF design enablement from leading analog IP suppliers and the Wireless SoC Platform Alliance (WISPA) consortium.
The RF platform is supported by an RF PDK specifically for the 65nm LPe process. The kit significantly reduces design time and helps ensure first-time-right silicon for full-featured SoCs with integrated RF.
It has been characterized and silicon-validated on the process on Chartered-manufactured silicon, and uses proven techniques from IBM to achieve a high degree of model-to-silicon accuracy. The PDK enables a more flexible methodology, based on a unique parameterized cell (p-cell) design approach that allows designers to tune RF components in a wide variety of ways.
The comprehensive PDK consists of a full palette of transistors and passives, including high fT RF transistors, vertical native (VNCAPs) and MIM capacitors, large tuning range MOS varactors, high Q-factor shielded inductor, precision poly resistors, and RF ESD devices.
These device solutions are complemented by RF-centric p-cells, an inductor synthesis kit, EM simulators setup files support and substrate noise analysis kit.
Single-chip RF solution
As consumer multi-media mobile applications continue to expand in features and functionality, integrated high-speed wired and wireless connectivity have become essential.
Combining high-speed wired and RF subsystems on a single SoC has been a challenge for most companies, historically forcing them to use the less favorable option of multiple-chip solutions that compromise cost and end-product form factor.
The RF platform from Chartered is intended to reduce the time, cost and risk associated with developing single-chip solutions that incorporate RF by making the latest process technology more accessible for those applications.
“The IBM Joint Development Alliance, known primarily for its advanced CMOS process technology development, has now added derivative technology development to the collaboration portfolio,” said Scottie Ginn, vice president of Design Enablement and Packaging, IBM Semiconductor Research and Development Center.
“We have invested heavily in developing a methodology that ensures the highest level of accuracy in RF design. Chartered has leveraged this RF methodology for its 65nm process to realize the full potential of the underlying process technology.”
In addition, a wide spectrum of IP support for RF applications is available for the 65nm RF platform. This includes silicon tested RF subsystems for WiFi, WiMax, and GPS; a host of industry standard interfaces (mDDR/DDR/DDR2, USB 2.0, PCI express, SATA II, and LVDS); and functional analog /mixed signal subsystems (Analog Front End, Audio CODEC, Video ADC/DAC, PLL/DLL, and baseband DAC/ADC).
Through Chartered’s participation in and support of the WISPA consortium, the 65nm RF process is backed by leading RF and SoC design services companies that can facilitate IP customization and software development via reference boards.
WISPA participants Socle Technology Corporation and Catena have worked together to develop a modular platform consisting of RF and baseband functions centered on hardened ARM9 and ARM11 microprocessor cores.
“By using the Chartered 65nm RF platform and RF PDK, all our silicon test chip measurements correlate extremely well with the simulation and we are able to achieve good progress with the system design in a very short time and with high confidence of getting the expected result.
"We believe that wireless connectivity will be commonplace in the mobile market and our goal is to make the integration of those wireless subsystems as accessible as possible so that product companies can focus on other phases of the hardware and software solution,” said Kave Kianush, CTO and vice president at Catena.
“Close collaboration with our partners and industry specialists in the RF and wireless ecosystem is essential to being able to offer a robust solution that addresses the needs of leading-edge mobile and wireless product developers.
"Combined with their specific capabilities and technology, our underlying process technology makes an ideal foundation for a market-ready integrated SoC platform. The silicon-verified mixed-signal/RF PDK serves to facilitate analog, mixed-signal and RF designs, RF SoC integration and verification,” said Dr. Shao-Fu “Sanford” Chu, vice president of device technology division, technology development at Chartered.
Enhanced 65nm low-power process
Chartered’s enhanced 65nm low-power process (65nm LPe) features multi-voltage threshold options for optimizing power and performance, and 4-9 metal layers to optimize die size requirements.
It offers support for a rich portfolio of RF and analog components, and is supported by a robust ecosystem of EDA tools and IP blocks, including a broad offering of standard cell and IO libraries from leading suppliers.
“The types of wireless-enabled products being developed by our mutual customers require a high level of IP integration to support the growing feature sets requested by consumers.
Chartered’s enhanced 65nm low-power technology delivers unique advantages by providing market-leading leakage benefits and support for a wide portfolio of proven IPs for SoC integration.
Socle’s expertise in ARM9 and ARM11 integration leverages the ecosystem supported on Chartered’s 65nm LPe platform and allows efficient customization of the feature set requested by a customer to bring its products to market faster and at lower risk,” said Chou-Te Kang, vice president of R&D at Socle.
The Chartered process offering, jointly developed with IBM, is based on Chartered’s enhanced 65nm low-power process (65nm LPe), and includes an IBM RF physical design kit (PDK) available from Chartered. This RF Platform comes with broad RF design enablement from leading analog IP suppliers and the Wireless SoC Platform Alliance (WISPA) consortium.
The RF platform is supported by an RF PDK specifically for the 65nm LPe process. The kit significantly reduces design time and helps ensure first-time-right silicon for full-featured SoCs with integrated RF.
It has been characterized and silicon-validated on the process on Chartered-manufactured silicon, and uses proven techniques from IBM to achieve a high degree of model-to-silicon accuracy. The PDK enables a more flexible methodology, based on a unique parameterized cell (p-cell) design approach that allows designers to tune RF components in a wide variety of ways.
The comprehensive PDK consists of a full palette of transistors and passives, including high fT RF transistors, vertical native (VNCAPs) and MIM capacitors, large tuning range MOS varactors, high Q-factor shielded inductor, precision poly resistors, and RF ESD devices.
These device solutions are complemented by RF-centric p-cells, an inductor synthesis kit, EM simulators setup files support and substrate noise analysis kit.
Single-chip RF solution
As consumer multi-media mobile applications continue to expand in features and functionality, integrated high-speed wired and wireless connectivity have become essential.
Combining high-speed wired and RF subsystems on a single SoC has been a challenge for most companies, historically forcing them to use the less favorable option of multiple-chip solutions that compromise cost and end-product form factor.
The RF platform from Chartered is intended to reduce the time, cost and risk associated with developing single-chip solutions that incorporate RF by making the latest process technology more accessible for those applications.
“The IBM Joint Development Alliance, known primarily for its advanced CMOS process technology development, has now added derivative technology development to the collaboration portfolio,” said Scottie Ginn, vice president of Design Enablement and Packaging, IBM Semiconductor Research and Development Center.
“We have invested heavily in developing a methodology that ensures the highest level of accuracy in RF design. Chartered has leveraged this RF methodology for its 65nm process to realize the full potential of the underlying process technology.”
In addition, a wide spectrum of IP support for RF applications is available for the 65nm RF platform. This includes silicon tested RF subsystems for WiFi, WiMax, and GPS; a host of industry standard interfaces (mDDR/DDR/DDR2, USB 2.0, PCI express, SATA II, and LVDS); and functional analog /mixed signal subsystems (Analog Front End, Audio CODEC, Video ADC/DAC, PLL/DLL, and baseband DAC/ADC).
Through Chartered’s participation in and support of the WISPA consortium, the 65nm RF process is backed by leading RF and SoC design services companies that can facilitate IP customization and software development via reference boards.
WISPA participants Socle Technology Corporation and Catena have worked together to develop a modular platform consisting of RF and baseband functions centered on hardened ARM9 and ARM11 microprocessor cores.
“By using the Chartered 65nm RF platform and RF PDK, all our silicon test chip measurements correlate extremely well with the simulation and we are able to achieve good progress with the system design in a very short time and with high confidence of getting the expected result.
"We believe that wireless connectivity will be commonplace in the mobile market and our goal is to make the integration of those wireless subsystems as accessible as possible so that product companies can focus on other phases of the hardware and software solution,” said Kave Kianush, CTO and vice president at Catena.
“Close collaboration with our partners and industry specialists in the RF and wireless ecosystem is essential to being able to offer a robust solution that addresses the needs of leading-edge mobile and wireless product developers.
"Combined with their specific capabilities and technology, our underlying process technology makes an ideal foundation for a market-ready integrated SoC platform. The silicon-verified mixed-signal/RF PDK serves to facilitate analog, mixed-signal and RF designs, RF SoC integration and verification,” said Dr. Shao-Fu “Sanford” Chu, vice president of device technology division, technology development at Chartered.
Enhanced 65nm low-power process
Chartered’s enhanced 65nm low-power process (65nm LPe) features multi-voltage threshold options for optimizing power and performance, and 4-9 metal layers to optimize die size requirements.
It offers support for a rich portfolio of RF and analog components, and is supported by a robust ecosystem of EDA tools and IP blocks, including a broad offering of standard cell and IO libraries from leading suppliers.
“The types of wireless-enabled products being developed by our mutual customers require a high level of IP integration to support the growing feature sets requested by consumers.
Chartered’s enhanced 65nm low-power technology delivers unique advantages by providing market-leading leakage benefits and support for a wide portfolio of proven IPs for SoC integration.
Socle’s expertise in ARM9 and ARM11 integration leverages the ecosystem supported on Chartered’s 65nm LPe platform and allows efficient customization of the feature set requested by a customer to bring its products to market faster and at lower risk,” said Chou-Te Kang, vice president of R&D at Socle.
Chartered begins production ramp of enhanced 65nm low-power process
SINGAPORE: Chartered Semiconductor Manufacturing announced the general availability of an enhanced version of its 65nm low-power (LP) process, called 65nm LPe.
The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent.
The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.
Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).
The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X.
This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.
A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.
The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.
Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.
Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency.
Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.
“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered.
“Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”
The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent.
The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.
Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).
The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X.
This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.
A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.
The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.
Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.
Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency.
Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.
“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered.
“Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”
Tuesday, 9 June 2009
Foundry semiconductor market to rise in Q2
EL SEGUNDO, USA: After three quarters of contraction, the pure-play foundry semiconductor manufacturing industry will enjoy robust growth in the second quarter—but how long will the good times last?
Global revenue for pure-play foundries, i.e., companies dedicated to producing semiconductors on behalf of other chipmakers, is set to rise to $3.6 billion in the second quarter, up 59.3 percent from $2.2 billion in the first. The increase follows a 1.8 percent sequential decrease in the third quarter of 2008, a 32.3 percent decline in the fourth quarter of 2008 and a 38.2 percent plunge in the first quarter of 2009.
“The foundry market in the second quarter is benefitting from both a major reduction in semiconductor inventories throughout the electronics supply chain and innovative new designs requiring innovative technology,” said Len Jelinek, director and principal analyst, semiconductor manufacturing, for iSuppli Corp. “However, while this growth will come as a relief to the foundries, it will not result in 2009 being a growth year for the foundry industry. Sustainable semiconductor growth will come only when the global economy recovers and consumers return to more normal patterns of purchases.”
For all of 2009, the pure-play foundry market will underperform the overall semiconductor industry, with foundries suffering a revenue decline of 26.5 percent.
Q1 catastrophe
Global pure-play foundry revenue in the first quarter of 2009 fell by 57.7 percent from $5.3 billion in the first quarter of 2008.
The foundry market’s disastrous performance in the first quarter was reflected in the weak results of the Top-10 players, nine of which suffered double-digit percentage declines in revenue, both on a sequential and a year-over-year basis.
The table presents iSuppli’s ranking of the world’s Top-10 pure-play foundries in the first quarter.
iSuppli Table: Worldwide Pure-Play Foundry Ranking for Q1 2009 (Ranking by Revenue in Millions of US Dollars)
Source: iSuppli, June 2009
The best performers among the Top-10 were Chartered Semiconductor and the newly-combined Tower Semiconductor Ltd. and Jazz Semiconductor Inc.
No.-3 ranked Chartered managed to outperform the overall foundry market by limiting its year-over-year sales decline to 43.4 percent. Company market share increased to 11.3 percent in the first quarter of 2009, up 2.8 points from 8.5 percent during the same period in 2008.
Tower’s revenue remained flat compared to a year earlier, allowing the company to expand its share by 1.5 points to 2.6 percent, up from 1.1 percent in the first quarter of 2008.
“Chartered’s and Tower’s relatively strong performances in the first quarter were due to acquisitions that expanded their revenue, rather than organic growth,” Jelinek said.
Chartered purchased an 8-inch manufacturing facility previously operated by Hitachi Semiconductor, while Tower acquired Jazz.
“Although 2009 will continue to be a challenging year for pure-play foundries, those companies that took aggressive actions to strategically prepare for the future in the second half of 2008 will emerge with increased market share and financial strength,” Jelinek said.
Global revenue for pure-play foundries, i.e., companies dedicated to producing semiconductors on behalf of other chipmakers, is set to rise to $3.6 billion in the second quarter, up 59.3 percent from $2.2 billion in the first. The increase follows a 1.8 percent sequential decrease in the third quarter of 2008, a 32.3 percent decline in the fourth quarter of 2008 and a 38.2 percent plunge in the first quarter of 2009.
“The foundry market in the second quarter is benefitting from both a major reduction in semiconductor inventories throughout the electronics supply chain and innovative new designs requiring innovative technology,” said Len Jelinek, director and principal analyst, semiconductor manufacturing, for iSuppli Corp. “However, while this growth will come as a relief to the foundries, it will not result in 2009 being a growth year for the foundry industry. Sustainable semiconductor growth will come only when the global economy recovers and consumers return to more normal patterns of purchases.”
For all of 2009, the pure-play foundry market will underperform the overall semiconductor industry, with foundries suffering a revenue decline of 26.5 percent.
Q1 catastrophe
Global pure-play foundry revenue in the first quarter of 2009 fell by 57.7 percent from $5.3 billion in the first quarter of 2008.
The foundry market’s disastrous performance in the first quarter was reflected in the weak results of the Top-10 players, nine of which suffered double-digit percentage declines in revenue, both on a sequential and a year-over-year basis.
The table presents iSuppli’s ranking of the world’s Top-10 pure-play foundries in the first quarter.
iSuppli Table: Worldwide Pure-Play Foundry Ranking for Q1 2009 (Ranking by Revenue in Millions of US Dollars)
Source: iSuppli, June 2009The best performers among the Top-10 were Chartered Semiconductor and the newly-combined Tower Semiconductor Ltd. and Jazz Semiconductor Inc.
No.-3 ranked Chartered managed to outperform the overall foundry market by limiting its year-over-year sales decline to 43.4 percent. Company market share increased to 11.3 percent in the first quarter of 2009, up 2.8 points from 8.5 percent during the same period in 2008.
Tower’s revenue remained flat compared to a year earlier, allowing the company to expand its share by 1.5 points to 2.6 percent, up from 1.1 percent in the first quarter of 2008.
“Chartered’s and Tower’s relatively strong performances in the first quarter were due to acquisitions that expanded their revenue, rather than organic growth,” Jelinek said.
Chartered purchased an 8-inch manufacturing facility previously operated by Hitachi Semiconductor, while Tower acquired Jazz.
“Although 2009 will continue to be a challenging year for pure-play foundries, those companies that took aggressive actions to strategically prepare for the future in the second half of 2008 will emerge with increased market share and financial strength,” Jelinek said.
Chartered Semi buys RAVE's Rhazer haze removal system
DELRAY BEACH, USA: RAVE LLC announced receipt of a purchase order for its new Rhazer haze removal system from one of the world's leading dedicated semiconductor foundries, Chartered Semiconductor Manufacturing Ltd, Singapore.
RAVE unveiled the Rhazer system in 2008 with a breakthrough dry process for the non-invasive removal of haze contamination from advanced photomasks.
Chartered has been evaluating the potential of the Rhazer technology since early 2009. The company elected to collaborate with RAVE as production beta partner to implement the Rhazer haze management system and process at Chartered's Fab 7 wafer production line in Singapore.
RAVE CEO, Barry Hopkins, stated: "We are very pleased to be working with the Chartered engineering team. The foundry wafer fabrication environment is particularly well suited for the Rhazer technology. The RAVE team has developed an excellent working relationship and professional respect for the Chartered team and the organization. We are looking forward to a highly favorable opportunity for both companies."
Chartered Fab 7 Reticle Management Team, who has been aggressively evaluating the system over the past few months added: "Our investigation concluded RAVE's Rhazer haze removal system works "as advertised" and we expect this new haze mitigation technology to bring significant time and cost savings to our photomask clean and control program."
RAVE unveiled the Rhazer system in 2008 with a breakthrough dry process for the non-invasive removal of haze contamination from advanced photomasks.
Chartered has been evaluating the potential of the Rhazer technology since early 2009. The company elected to collaborate with RAVE as production beta partner to implement the Rhazer haze management system and process at Chartered's Fab 7 wafer production line in Singapore.
RAVE CEO, Barry Hopkins, stated: "We are very pleased to be working with the Chartered engineering team. The foundry wafer fabrication environment is particularly well suited for the Rhazer technology. The RAVE team has developed an excellent working relationship and professional respect for the Chartered team and the organization. We are looking forward to a highly favorable opportunity for both companies."
Chartered Fab 7 Reticle Management Team, who has been aggressively evaluating the system over the past few months added: "Our investigation concluded RAVE's Rhazer haze removal system works "as advertised" and we expect this new haze mitigation technology to bring significant time and cost savings to our photomask clean and control program."
Friday, 25 April 2008
Encouraging developments in 22nm!
Suddenly, but steadily, there seems to be lot of work going on in the 22nm space. This can only be encouraging for the global semiconductor industry.
Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.
According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.
The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon "fin".
Early this month, Chartered Semiconductor Manufacturing, one of the world's top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.
IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.
And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.
PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.
Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.
He said: "The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower."
Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.
Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.
According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.
The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon "fin".
Early this month, Chartered Semiconductor Manufacturing, one of the world's top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.
IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.
And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.
PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.
Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.
He said: "The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower."
Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.
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