GARCHING/MUNICH, GERMANY: SUSS MicroTec, a supplier of innovative process and test solutions for the semiconductor industry and related markets, has shipped a LithoPack300 lithography cluster to Japan.
The system has been successfully installed at the customer site where it will be used for 3D integration technology development. The cluster solution with coat, bake, expose and develop modules for wafers up to 300mm constitutes a cost-efficient approach for the challenging Through-Silicon-Via (TSV) manufacturing and backside redistribution layer (RDL) in 3D integration production.
With this integrated lithography solution and further solutions for permanent and temporary wafer bonding SUSS MicroTec offers a complete process and technology portfolio for 3D integration. SUSS MicroTec has recently announced its participation in a range of research projects on 3D integration processes driving technology advances from the equipment supplier side.
The LithoPack300 combines two 300mm photolithography modules in one system and represents the most cost-efficient integrated lithography solution in the market. The MA300 Gen2 module, a 300mm next generation mask aligner platform, provides excellent back-side processing capabilities that enable highly accurate photolithography processes for the manufacturing of back side redistribution layers or TSV etch masks.
The ACS300 module offers closed cover coating technology and best-in-class edge bead removal precision and therefore enables optimum thick resist processing for 3D integration processes.
“In recent years SUSS MicroTec lithography systems have developed into an enabling platform for next generation 3D Integration technologies”, said Rolf Wolf, general manager of SUSS MicroTec’s lithography division. “Today SUSS Mask Aligners can be enhanced with tooling for submicron alignment, wafer edge handling or UV-bonding for wafer to wafer stacking, all features that have become critically important for 3D applications.
“With the involvement of SUSS MicroTec in international research cooperations we are proud to become further involved in 3D integration process development.” said Raymond Lau, Business Manager for SUSS MicroTec in Japan.
“Our Japanese customers will directly benefit from these technical advances. We enjoy being able to offer a well-engineered solution portfolio for 3D integration that really meets their specific needs.”
Showing posts with label lithography. Show all posts
Showing posts with label lithography. Show all posts
Tuesday, 25 August 2009
Tuesday, 14 July 2009
ASML intros holistic lithography solutions to continue Moore’s Law
SAN FRANCISCO, USA: ASML Holding NV has unveiled new lithography products that allow chipmakers to continue to shrink features on semiconductors.
As part of ASML’s Holistic Lithography vision, FlexRay programmable illumination and BaseLiner scanner stability optimize and stabilize manufacturing process windows.
The semiconductor industry is driven by shrink that reduces manufacturing cost and improves device performance. However, as semiconductor feature sizes shrink, so do process windows -- the accuracy tolerances necessary to produce viable chips - imposing extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU).
“Historically chipmakers have optimized the various manufacturing steps independent of one another. As we move to the 32-nm node and smaller, independent optimization is no longer enough,” said Bert Koek, senior vice president, applications product group at ASML.
“By intelligently integrating computational lithography, wafer lithography and process control, we provide a holistic approach that enables shrink by optimizing process windows and lithography system set-up for volume manufacturing.”
During the chip design phase ASML’s holistic lithography uses actual scanner profiles and tuning capabilities to create a design with the maximum process window for a given node and application.
Jim Koonmen, general manager for Brion Technologies said, “We announced Tachyon SMO (source-mask optimization) in February of this year. Today’s FlexRay announcement introduces technology that provides flexibility in pupil shape and offers extra degrees of freedom in design. The integration of Tachyon SMO and FlexRay provides unmatched co-optimization of mask and illumination source for the largest possible process window.”
During manufacturing, ASML holistic lithography leverages unique metrology techniques and feedback loops to monitor overlay and CDU performance to continuously maintain the system centered in the process window. BaseLiner enables optimized process windows and higher yields by keeping scanner performance to a pre-defined baseline condition.
Tachyon SMO, FlexRay and BaseLiner are just three of the many products ASML offers as part of Eclipse holistic lithography packages. Each Eclipse package is tailored to a specific customer, node and application.
As part of ASML’s Holistic Lithography vision, FlexRay programmable illumination and BaseLiner scanner stability optimize and stabilize manufacturing process windows.
The semiconductor industry is driven by shrink that reduces manufacturing cost and improves device performance. However, as semiconductor feature sizes shrink, so do process windows -- the accuracy tolerances necessary to produce viable chips - imposing extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU).
“Historically chipmakers have optimized the various manufacturing steps independent of one another. As we move to the 32-nm node and smaller, independent optimization is no longer enough,” said Bert Koek, senior vice president, applications product group at ASML.
“By intelligently integrating computational lithography, wafer lithography and process control, we provide a holistic approach that enables shrink by optimizing process windows and lithography system set-up for volume manufacturing.”
During the chip design phase ASML’s holistic lithography uses actual scanner profiles and tuning capabilities to create a design with the maximum process window for a given node and application.
Jim Koonmen, general manager for Brion Technologies said, “We announced Tachyon SMO (source-mask optimization) in February of this year. Today’s FlexRay announcement introduces technology that provides flexibility in pupil shape and offers extra degrees of freedom in design. The integration of Tachyon SMO and FlexRay provides unmatched co-optimization of mask and illumination source for the largest possible process window.”
During manufacturing, ASML holistic lithography leverages unique metrology techniques and feedback loops to monitor overlay and CDU performance to continuously maintain the system centered in the process window. BaseLiner enables optimized process windows and higher yields by keeping scanner performance to a pre-defined baseline condition.
Tachyon SMO, FlexRay and BaseLiner are just three of the many products ASML offers as part of Eclipse holistic lithography packages. Each Eclipse package is tailored to a specific customer, node and application.
Monday, 13 July 2009
ASML, Cymer announce advancement in EUV
VELDHOVEN, THE NETHERLANDS & SAN DIEGO, USA: ASML and Cymer Inc. formally announced the shipment of the world's first fully integrated laser-produced plasma (LPP) Extreme Ultraviolet (EUV) lithography source to ASML.
Cymer's EUV source, the first of a multi-unit purchase agreement between the two companies, is currently being installed at ASML's Veldhoven headquarters where it will support integration and testing of next generation EUV lithography scanners.
Together with this shipment, Cymer announces achieving a record milestone of 75 Watts of EUV lithography exposure power (full die exposure) and expects to scale to 100 Watts exposure power within the current quarter, enabling scanner throughput of 60 silicon wafers (300 mm/12 inch) per hour which is required for volume manufacturing with ASML’s EUV technology.
First shipments of production-capable EUV scanners from ASML are planned a year from now. The source concept will be capable of scaling over time to performance levels consistent with exposing more than 100 wafers per hour when fully integrated into ASML scanners.
EUV is a new lithographic method using a 15 times shorter wavelength than current lithography systems, enabling semiconductor scaling to resolutions of 10 nanometers (nm) and smaller. EUV will support Moore’s Law –- the trend towards more powerful, energy-efficient yet affordable chips -- for at least another 10 years.
“Our team has worked hard to ship the industry's first LPP EUV lithography source while achieving new levels of EUV power,” said Bob Akins, chief executive officer of Cymer.
“We are pleased to be partnering with ASML in the advancement of EUV lithography, which will offer high-resolution, high-throughput, manufacturing capability for the production of advanced ICs with critical dimensions below 22nm, enabling the continuation of Moore'’s Law for multiple chip generations to come. Within the next few years, chips patterned by EUV lithography will be hundreds of times more powerful than today’s”, concluded Akins.
“Cymer and ASML are committed to bringing EUV lithography to production reality for chip makers worldwide,” added Martin van den Brink, executive vice president of Products and Technology at ASML.
“EUV is by far the most cost-effective volume lithography technology for more powerful future generations of semiconductors, and our achievements show how the equipment industry is making huge strides to the introduction of the first production-ready EUV lithography tools in 2010. This revolutionary new architecture provides chip makers with technology that will extend the semiconductor shrink for another decade at least.”
An LPP EUV lithography source, which produces "light" with 13.5 nm wavelength (invisible to the human eye), represents a significant technology paradigm shift from today's Deep Ultraviolet (DUV) lithography excimer laser sources.
In an LPP EUV source, microscopic droplets of molten tin are fired through a vacuum chamber and individually tracked and vaporized by a pulsed high power infrared laser -- as frequently as 50,000 times per second -- creating a high temperature tin plasma point source which radiates 13.5 nm wavelength light.
A large EUV mirror collects and directs this light into the scanner where it is patterned by a photomask and projected using a complex set of image reduction mirrors onto a light-sensitive silicon wafer - transferring the pattern onto the wafer.
ASML has received orders for five EUV lithographic systems from memory and logic customers on three continents, with deliveries starting in 2010.
Cymer's EUV source, the first of a multi-unit purchase agreement between the two companies, is currently being installed at ASML's Veldhoven headquarters where it will support integration and testing of next generation EUV lithography scanners.
Together with this shipment, Cymer announces achieving a record milestone of 75 Watts of EUV lithography exposure power (full die exposure) and expects to scale to 100 Watts exposure power within the current quarter, enabling scanner throughput of 60 silicon wafers (300 mm/12 inch) per hour which is required for volume manufacturing with ASML’s EUV technology.
First shipments of production-capable EUV scanners from ASML are planned a year from now. The source concept will be capable of scaling over time to performance levels consistent with exposing more than 100 wafers per hour when fully integrated into ASML scanners.
EUV is a new lithographic method using a 15 times shorter wavelength than current lithography systems, enabling semiconductor scaling to resolutions of 10 nanometers (nm) and smaller. EUV will support Moore’s Law –- the trend towards more powerful, energy-efficient yet affordable chips -- for at least another 10 years.
“Our team has worked hard to ship the industry's first LPP EUV lithography source while achieving new levels of EUV power,” said Bob Akins, chief executive officer of Cymer.
“We are pleased to be partnering with ASML in the advancement of EUV lithography, which will offer high-resolution, high-throughput, manufacturing capability for the production of advanced ICs with critical dimensions below 22nm, enabling the continuation of Moore'’s Law for multiple chip generations to come. Within the next few years, chips patterned by EUV lithography will be hundreds of times more powerful than today’s”, concluded Akins.
“Cymer and ASML are committed to bringing EUV lithography to production reality for chip makers worldwide,” added Martin van den Brink, executive vice president of Products and Technology at ASML.
“EUV is by far the most cost-effective volume lithography technology for more powerful future generations of semiconductors, and our achievements show how the equipment industry is making huge strides to the introduction of the first production-ready EUV lithography tools in 2010. This revolutionary new architecture provides chip makers with technology that will extend the semiconductor shrink for another decade at least.”
An LPP EUV lithography source, which produces "light" with 13.5 nm wavelength (invisible to the human eye), represents a significant technology paradigm shift from today's Deep Ultraviolet (DUV) lithography excimer laser sources.
In an LPP EUV source, microscopic droplets of molten tin are fired through a vacuum chamber and individually tracked and vaporized by a pulsed high power infrared laser -- as frequently as 50,000 times per second -- creating a high temperature tin plasma point source which radiates 13.5 nm wavelength light.
A large EUV mirror collects and directs this light into the scanner where it is patterned by a photomask and projected using a complex set of image reduction mirrors onto a light-sensitive silicon wafer - transferring the pattern onto the wafer.
ASML has received orders for five EUV lithographic systems from memory and logic customers on three continents, with deliveries starting in 2010.
Monday, 15 June 2009
Semicon equipment industry outlook bottomed out in Q2-09
STAMFORD, USA: The outlook for the semiconductor equipment industry is beginning to improve, as it appears capital equipment spending has bottomed out in the second quarter of 2009, according to Gartner Inc. Analysts predict a gradual improvement on a quarter-by-quarter basis throughout the rest of the year and into 2010.
The current uptick in semiconductor sales will not be sufficient to overcome the effects of industry-wide overcapacity and low utilization rates in the short term. Worldwide semiconductor capital spending is on pace to total $24.3 billion in 2009, a 44.8 percent decline from 2008 spending of $44 billion (see Table 1). In 2010, worldwide capital equipment spending is forecast to reach $29.4 billion, a 20.9 percent increase from 2009.
“The impact of the economic crisis has hit the semiconductor equipment industry hard, but signs of life are returning,” said Klaus Rinnen, managing vice president at Gartner. “Undoubtedly it will be a long, slow road to complete recovery, but we are seeing the first indications of increased foundry activity to replenish inventories depleted by the cutbacks of the past few quarters.”
Table 1
Worldwide Semiconductor Capital Equipment Spending Forecast, 2008-2013 (Millions of Dollars)
Source: Gartner (June 2009)
Worldwide wafer fab equipment spending is expected to decrease 47.1 percent in 2009, following a drop of nearly 33 percent in 2008. In 2009, the etch, clean and planarization segments will be the largest of the front-end equipment areas, followed by deposition and then by lithography. Lithography has been hit especially hard by the downturn as sales for the most advanced 193nm immersion tools in memory have been lukewarm, with capital spending for memory at levels not seen since 2002.
After declining nearly 25 percent last year, the packaging and assembly equipment (PAE) market is expected to fall nearly 47 percent in 2009. A recovery for PAE is likely to be seen in the second half of this year if recent positive economic developments are sustained.
For 2009, the worldwide automated test equipment (ATE) market is forecast to decline 32 percent. While the test market has waded through a difficult period since 2007, it appears that a bottom is forming in the second quarter of 2009. The ATE market now sits at very low market levels, with some test segments very likely realizing substantial capacity reductions. As the industry moves toward a growth phase, the potential for explosive growth in the 2010 and 2011 time frame could be realized.
Rinnen said that overall, the industry has responded as it should when faced with one of the worst downturns in its history —- by eliminating all unnecessary spending, cutting purchases to inventories and not doing anything dramatic. He recommended that for the next few quarters, equipment suppliers focus on quarter-to-quarter growth and let the annual numbers fall where they may.
“Over the past few years, we have seen the semiconductor and electronics industries implement impressive movements in their ability to control and manage inventories,” said Mr. Rinnen. “It appears the industry has learned a painful lesson and can implement improvements on its ability to manage capital investments and capacity and thus bring a return to profitability to all segments.”
The current uptick in semiconductor sales will not be sufficient to overcome the effects of industry-wide overcapacity and low utilization rates in the short term. Worldwide semiconductor capital spending is on pace to total $24.3 billion in 2009, a 44.8 percent decline from 2008 spending of $44 billion (see Table 1). In 2010, worldwide capital equipment spending is forecast to reach $29.4 billion, a 20.9 percent increase from 2009.
“The impact of the economic crisis has hit the semiconductor equipment industry hard, but signs of life are returning,” said Klaus Rinnen, managing vice president at Gartner. “Undoubtedly it will be a long, slow road to complete recovery, but we are seeing the first indications of increased foundry activity to replenish inventories depleted by the cutbacks of the past few quarters.”
Table 1
Worldwide Semiconductor Capital Equipment Spending Forecast, 2008-2013 (Millions of Dollars)
Source: Gartner (June 2009)Worldwide wafer fab equipment spending is expected to decrease 47.1 percent in 2009, following a drop of nearly 33 percent in 2008. In 2009, the etch, clean and planarization segments will be the largest of the front-end equipment areas, followed by deposition and then by lithography. Lithography has been hit especially hard by the downturn as sales for the most advanced 193nm immersion tools in memory have been lukewarm, with capital spending for memory at levels not seen since 2002.
After declining nearly 25 percent last year, the packaging and assembly equipment (PAE) market is expected to fall nearly 47 percent in 2009. A recovery for PAE is likely to be seen in the second half of this year if recent positive economic developments are sustained.
For 2009, the worldwide automated test equipment (ATE) market is forecast to decline 32 percent. While the test market has waded through a difficult period since 2007, it appears that a bottom is forming in the second quarter of 2009. The ATE market now sits at very low market levels, with some test segments very likely realizing substantial capacity reductions. As the industry moves toward a growth phase, the potential for explosive growth in the 2010 and 2011 time frame could be realized.
Rinnen said that overall, the industry has responded as it should when faced with one of the worst downturns in its history —- by eliminating all unnecessary spending, cutting purchases to inventories and not doing anything dramatic. He recommended that for the next few quarters, equipment suppliers focus on quarter-to-quarter growth and let the annual numbers fall where they may.
“Over the past few years, we have seen the semiconductor and electronics industries implement impressive movements in their ability to control and manage inventories,” said Mr. Rinnen. “It appears the industry has learned a painful lesson and can implement improvements on its ability to manage capital investments and capacity and thus bring a return to profitability to all segments.”
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