LOS ALTOS, USA: Rambus Inc. has showcased a silicon demonstration of a complete XDR™ memory system running at data rates up to 7.2Gbps with superior power efficiency.
This silicon demonstration consists of Elpida’s recently-announced 1Gb XDR DRAM device and an XIO memory controller transmitting realistic data patterns. The XIO memory controller is up to 3.5 times more power efficient than a GDDR5 controller, and the total memory system can provide up to two times more bandwidth than GDDR5 at equivalent power.
In addition, the XIO memory controller demonstrated bi-modal operation with support for both XDR DRAM as well as next-generation XDR2 DRAM.
“Future graphics and multi-core processors require significantly higher memory performance under extremely challenging power and thermal constraints,” said Martin Scott, senior vice president of Research and Technology Development at Rambus. “This technology demonstration highlights the outstanding power efficiency of the XDR and XDR2 memory architectures at performance levels from 3.2 to 7.2Gbps with scalability to well over 10Gbps.”
This silicon demonstration, shown at Denali MemCon 2009 in San Jose, is the first implementation supporting the XDR memory architecture roadmap incorporating innovations developed as part of Rambus’ Terabyte Bandwidth Initiative. Implemented in the bi-modal XIO memory controller for XDR2 operation, these innovations include:
* Fully Differential Memory Architecture (FDMA) – enhances signal integrity and increases performance through point-to-point differential signaling of clock, data, and command/address (C/A), an industry first;
* FlexLink™ C/A – reduces pin count and increases scalability; and
* Enhanced FlexPhase™ – enables the world’s highest memory signaling rates while simplifying routing and board design.
In addition, the XDR2 memory architecture includes:
* Micro-threading of the DRAM core – introduced by Rambus in early 2005, increases data transfer efficiency and reduces power consumption; and
* 16X Data Rate – allows for extremely high data rates with the use of a relatively low-speed system clock.
Built on these innovations, an XDR2 memory system can provide memory bandwidths of over 500GB/s to an SoC. A single 4Byte-wide, 9.6Gbps XDR2 DRAM device can deliver up to 38.4GB/s of peak bandwidth, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s.
With these capabilities, the XDR and XDR2 memory architectures are scalable across a broad range of performance appropriate for multi-core computing, graphics, gaming, and consumer electronics.
The XDR memory architecture has already been adopted in products including the Sony PLAYSTATION computer entertainment system, DLP projectors, Teradici PC-over-IP computing systems, and Toshiba’s Qosmio® laptop PCs and HDTV chipsets.
Showing posts with label Rambus. Show all posts
Showing posts with label Rambus. Show all posts
Tuesday, 23 June 2009
Friday, 12 June 2009
Rambus reaches tentative settlement with EC
LOS ALTOS, USA: Rambus Inc., one of the world’s premier technology licensing companies specializing in high-speed memory architectures, announced that it has reached a tentative settlement with the European Commission to resolve the pending case against the company.
Under the proposed resolution, the Commission would make no finding of liability relative to JEDEC-related charges, and no fine would be assessed against Rambus. In addition, Rambus would commit to offer licenses with maximum royalty rates for certain memory types and memory controllers on a forward-going basis.
European Commission antitrust procedures stipulate that a final decision must be preceded by a consultation of interested third parties on the terms of the commitments offered (the “Commitment”); this consultation was initiated.
“Our view regarding standard-setting organizations is that the rules of such organizations must be written and clear, and that there should be consequences if such clear written rules are violated,” said Thomas Lavelle, senior vice president and general counsel at Rambus.
“We did nothing wrong during our participation in the JEDEC standard-setting organization, as demonstrated in multiple U.S. court victories including before the DC Court of Appeals. With this proposed resolution, we create a new platform where all parties can move forward by licensing our patented innovations for future use in their products rather than engaging in costly litigation.”
Under the proposed resolution, Rambus will offer licenses with maximum royalty rates for five-year worldwide licenses of 1.5 percent for DDR2, DDR3, GDDR3 and GDDR4 SDRAM memory types. Licensees who ship less than 10 percent of their DRAM products in the older SDR and DDR DRAM types will enjoy a royalty holiday for those older types, subject to compliance with the terms of the license.
In addition, Rambus will offer licenses with maximum royalty rates for five-year worldwide licenses of 1.5 percent per unit for SDR memory controllers through April 2010, dropping to 1 percent thereafter, and royalty rates of 2.65 percent per unit for DDR, DDR2, DDR3, GDDR3 and GDDR4 memory controllers through April 2010, then dropping to 2 percent.
This commitment to license at the above rates will be valid for a period of five years from the adoption date of the Commitment decision. All royalty rates are applicable to future shipments only.
The European Commission originally brought charges against Rambus in August 2007 alleging violation of European Union competition law. The Commission’s investigation followed complaints set forth by certain DRAM manufacturers originating with Rambus’ 1992-1995 participation in an industry standard-setting organization, the Joint Electron Device Engineering Council (“JEDEC”).
Similar charges had been pursued by the Federal Trade Commission (FTC) in the United States. The FTC recently closed its investigation following a series of US Court rulings underlining that the allegations of Rambus’ wrongdoing were ill-founded.
Under the proposed resolution, the Commission would make no finding of liability relative to JEDEC-related charges, and no fine would be assessed against Rambus. In addition, Rambus would commit to offer licenses with maximum royalty rates for certain memory types and memory controllers on a forward-going basis.
European Commission antitrust procedures stipulate that a final decision must be preceded by a consultation of interested third parties on the terms of the commitments offered (the “Commitment”); this consultation was initiated.
“Our view regarding standard-setting organizations is that the rules of such organizations must be written and clear, and that there should be consequences if such clear written rules are violated,” said Thomas Lavelle, senior vice president and general counsel at Rambus.
“We did nothing wrong during our participation in the JEDEC standard-setting organization, as demonstrated in multiple U.S. court victories including before the DC Court of Appeals. With this proposed resolution, we create a new platform where all parties can move forward by licensing our patented innovations for future use in their products rather than engaging in costly litigation.”
Under the proposed resolution, Rambus will offer licenses with maximum royalty rates for five-year worldwide licenses of 1.5 percent for DDR2, DDR3, GDDR3 and GDDR4 SDRAM memory types. Licensees who ship less than 10 percent of their DRAM products in the older SDR and DDR DRAM types will enjoy a royalty holiday for those older types, subject to compliance with the terms of the license.
In addition, Rambus will offer licenses with maximum royalty rates for five-year worldwide licenses of 1.5 percent per unit for SDR memory controllers through April 2010, dropping to 1 percent thereafter, and royalty rates of 2.65 percent per unit for DDR, DDR2, DDR3, GDDR3 and GDDR4 memory controllers through April 2010, then dropping to 2 percent.
This commitment to license at the above rates will be valid for a period of five years from the adoption date of the Commitment decision. All royalty rates are applicable to future shipments only.
The European Commission originally brought charges against Rambus in August 2007 alleging violation of European Union competition law. The Commission’s investigation followed complaints set forth by certain DRAM manufacturers originating with Rambus’ 1992-1995 participation in an industry standard-setting organization, the Joint Electron Device Engineering Council (“JEDEC”).
Similar charges had been pursued by the Federal Trade Commission (FTC) in the United States. The FTC recently closed its investigation following a series of US Court rulings underlining that the allegations of Rambus’ wrongdoing were ill-founded.
Tuesday, 9 June 2009
Rambus XDR DRAM surpasses 100 million units shipped
LOS ALTOS, USA: Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed chip architectures, announced that its customers have shipped over 100 million XDR DRAM devices worldwide. XDR DRAM is part of a total memory solution developed by Rambus.
The award-winning XDR memory architecture achieves an order of magnitude higher performance than today's standard memories. With the flexibility to provide more bandwidth at better power efficiency per device than competing technologies, XDR memory both reduces overall systems costs and delivers the performance needed for the most advanced electronic products.
“Consumers’ demand for increasingly powerful graphics and computing applications require superior memory bandwidth and power efficiency,” said Sharon Holt, senior vice president of Licensing and Marketing at Rambus. “The XDR memory architecture has proven an ideal solution for a broad range of products needing blazing fast speeds and excellent power efficiency. No other memory technology provides the flexibility the XDR architecture offers to system and chip designers.”
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
Key components enabling the breakthrough performance of the XDR memory architecture are:
* XDR DRAM is a high-performance memory that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 7.2Gbps data rates providing up to 28.8GB/s of bandwidth with a single DRAM device.
* XIO controller IO cell provides the same high-speed signaling capability found on the DRAM, but adds additional enhancements like FlexPhase technology that eliminates the need for trace length matching.
* XMC memory controller is a fully synthesizable logical memory controller that is optimized to take advantage of innovations like Dynamic Point-to-Point which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
* XCG clock generator provides the system clocks with four programmable outputs and is guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices.
XDR DRAM is available fromleading memory suppliers Elpida and Samsung Electronics. It has been adopted in high-volume products, including the Sony PLAYSTATION3 computer entertainment system, DLP projectors, Teradici PC-over-IP computing systems, and Toshiba’s Qosmio laptop PCs and HDTV chipsets.
The award-winning XDR memory architecture achieves an order of magnitude higher performance than today's standard memories. With the flexibility to provide more bandwidth at better power efficiency per device than competing technologies, XDR memory both reduces overall systems costs and delivers the performance needed for the most advanced electronic products.
“Consumers’ demand for increasingly powerful graphics and computing applications require superior memory bandwidth and power efficiency,” said Sharon Holt, senior vice president of Licensing and Marketing at Rambus. “The XDR memory architecture has proven an ideal solution for a broad range of products needing blazing fast speeds and excellent power efficiency. No other memory technology provides the flexibility the XDR architecture offers to system and chip designers.”
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
Key components enabling the breakthrough performance of the XDR memory architecture are:
* XDR DRAM is a high-performance memory that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 7.2Gbps data rates providing up to 28.8GB/s of bandwidth with a single DRAM device.
* XIO controller IO cell provides the same high-speed signaling capability found on the DRAM, but adds additional enhancements like FlexPhase technology that eliminates the need for trace length matching.
* XMC memory controller is a fully synthesizable logical memory controller that is optimized to take advantage of innovations like Dynamic Point-to-Point which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
* XCG clock generator provides the system clocks with four programmable outputs and is guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices.
XDR DRAM is available fromleading memory suppliers Elpida and Samsung Electronics. It has been adopted in high-volume products, including the Sony PLAYSTATION3 computer entertainment system, DLP projectors, Teradici PC-over-IP computing systems, and Toshiba’s Qosmio laptop PCs and HDTV chipsets.
Tuesday, 26 May 2009
Rambus unveils new innovations for main memory
LOS ALTOS, USA: Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, has unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps.
These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies. Through this collection of innovations, designers can achieve higher memory data rates, higher effective throughput, better power efficiency and the increased capacity necessary for future computing applications.
"Product advancements in multi-core computing, virtualization and chip integration put ever-increasing demands on the memory sub-system, a key performance limiter in today’s performance computing systems," said Craig Hampel, Rambus Fellow. "This collection of breakthrough innovations from Rambus allows for memory systems that are better suited for the bandwidth and workloads of these throughput-oriented multi-core processors, increasing the design and solution space for future main memory to enable a new generation of computing platforms."
The Rambus key innovations to advance the main memory roadmap include:
* FlexPhase Technology -- introduced in the XDR memory architecture, can enable higher data rates compared to direct strobing technology used in DDR3;
* Near Ground Signaling -- supports high performance at greatly reduced IO power, allowing operation at 0.5V while still maintaining robust signal integrity;
* FlexClocking Architecture -- introduced in Rambus’ Mobile Memory Initiative, reduces clocking power by eliminating the need for a DLL or PLL on the DRAM;
* Module Threading -- increases memory efficiency and reduces DRAM core power, and when combined with Near Ground Signaling and FlexClocking technology, can cut total memory system power by over 40 percent;
* Dynamic Point-to-Point (DPP) -- provides a path for capacity upgrades without compromising performance through robust point-to-point signaling.
These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies. Through this collection of innovations, designers can achieve higher memory data rates, higher effective throughput, better power efficiency and the increased capacity necessary for future computing applications.
"Product advancements in multi-core computing, virtualization and chip integration put ever-increasing demands on the memory sub-system, a key performance limiter in today’s performance computing systems," said Craig Hampel, Rambus Fellow. "This collection of breakthrough innovations from Rambus allows for memory systems that are better suited for the bandwidth and workloads of these throughput-oriented multi-core processors, increasing the design and solution space for future main memory to enable a new generation of computing platforms."
The Rambus key innovations to advance the main memory roadmap include:
* FlexPhase Technology -- introduced in the XDR memory architecture, can enable higher data rates compared to direct strobing technology used in DDR3;
* Near Ground Signaling -- supports high performance at greatly reduced IO power, allowing operation at 0.5V while still maintaining robust signal integrity;
* FlexClocking Architecture -- introduced in Rambus’ Mobile Memory Initiative, reduces clocking power by eliminating the need for a DLL or PLL on the DRAM;
* Module Threading -- increases memory efficiency and reduces DRAM core power, and when combined with Near Ground Signaling and FlexClocking technology, can cut total memory system power by over 40 percent;
* Dynamic Point-to-Point (DPP) -- provides a path for capacity upgrades without compromising performance through robust point-to-point signaling.
Hynix to post $397 million for infringing Rambus patents
LOS ALTOS, USA: Rambus Inc. announced that the US District Court for the Northern District of California has ordered Hynix Semiconductor to secure the judgment amount of approximately $397 million through a combination of a bond and a lien on a Hynix property in South Korea for infringing Rambus patents.
The bonded amount of $250 million is required to be posted within 45 days of the order. The lien will only serve as security if a new appraisal of the Hynix property shows a fair market value of at least double the amount of the judgment not secured by the bond. If the appraisal is inadequate, Rambus may ask the Court to substitute other security.
Final judgment in this matter was entered against Hynix on March 10, 2009 in the amount of approximately $134 million for infringement through December 31, 2005 and approximately $215 million for its infringement from January 1, 2006 through January 31, 2009. In addition, the Court awarded about $48M in pre-judgment interest to Rambus.
“We fully expect the judgment against Hynix to be upheld on appeal, and that we will be entitled to collect the entire amount of the judgment,” said Thomas Lavelle, senior vice president and general counsel at Rambus. “We appreciate the Court’s thoughtful consideration in this case, however, we believe Hynix should have been required to post a bond for the entire amount of the judgment. If Hynix’s proposed lien fails to show value of roughly $300 million, we will ask the Court for other security in order to protect Rambus’ interests.”
In addition, the Court ordered Hynix to pay compulsory license fees into escrow pending the outcome of the appeal Hynix filed in this matter. The Court ordered Hynix to pay Rambus royalties on net sales after January 31, 2009 and before April 18, 2010 of 1 percent for SDR SDRAM and 4.25 percent for DDR SDRAM memory devices.
The latter rate applies to DDR, DDR2, DDR3, GDDR, gDDR2 and GDDR3 SDRAM devices, as well as DDR SGRAM devices. Damages and the compulsory license apply to US infringements of the patent claims in suit.
Background of the case
This case was originally filed by Hynix against Rambus in August 2000. The Honorable Ronald M. Whyte of the U.S. District Court for the Northern District of California split the case into three separate phases with Rambus subsequently prevailing in all three phases.
During the first phase, Hynix alleged that Rambus’ patents were invalid based on the doctrine of unclean hands. The Court issued its Findings of Fact and Conclusions of Law in Rambus’ favor in January 2006. The Court reaffirmed its finding of no spoliation when it denied Hynix’s motion for reconsideration in February 2009.
The second phase dealt with Rambus’ allegations that Hynix memory products infringed its patents. In April 2006, a jury unanimously found that all 10 Rambus patent claims at issue in that trial are valid and infringed by Hynix memory products. The jury award of approximately $307 million in damages for US sales of infringing Hynix products through December 31, 2005, was subsequently reduced by the Court to approximately $134 million.
In the third and final phase of the case, Hynix (together with Micron and Nanya) tried its remaining claims and defenses against Rambus including antitrust and fraud claims based on Rambus’ participation in a standard-setting organization called JEDEC. In March 2008, a jury found Rambus had acted properly during its participation in JEDEC in the early 1990s. The Court similarly found in Rambus’ favor in a decision issued on March 3, 2009.
The bonded amount of $250 million is required to be posted within 45 days of the order. The lien will only serve as security if a new appraisal of the Hynix property shows a fair market value of at least double the amount of the judgment not secured by the bond. If the appraisal is inadequate, Rambus may ask the Court to substitute other security.
Final judgment in this matter was entered against Hynix on March 10, 2009 in the amount of approximately $134 million for infringement through December 31, 2005 and approximately $215 million for its infringement from January 1, 2006 through January 31, 2009. In addition, the Court awarded about $48M in pre-judgment interest to Rambus.
“We fully expect the judgment against Hynix to be upheld on appeal, and that we will be entitled to collect the entire amount of the judgment,” said Thomas Lavelle, senior vice president and general counsel at Rambus. “We appreciate the Court’s thoughtful consideration in this case, however, we believe Hynix should have been required to post a bond for the entire amount of the judgment. If Hynix’s proposed lien fails to show value of roughly $300 million, we will ask the Court for other security in order to protect Rambus’ interests.”
In addition, the Court ordered Hynix to pay compulsory license fees into escrow pending the outcome of the appeal Hynix filed in this matter. The Court ordered Hynix to pay Rambus royalties on net sales after January 31, 2009 and before April 18, 2010 of 1 percent for SDR SDRAM and 4.25 percent for DDR SDRAM memory devices.
The latter rate applies to DDR, DDR2, DDR3, GDDR, gDDR2 and GDDR3 SDRAM devices, as well as DDR SGRAM devices. Damages and the compulsory license apply to US infringements of the patent claims in suit.
Background of the case
This case was originally filed by Hynix against Rambus in August 2000. The Honorable Ronald M. Whyte of the U.S. District Court for the Northern District of California split the case into three separate phases with Rambus subsequently prevailing in all three phases.
During the first phase, Hynix alleged that Rambus’ patents were invalid based on the doctrine of unclean hands. The Court issued its Findings of Fact and Conclusions of Law in Rambus’ favor in January 2006. The Court reaffirmed its finding of no spoliation when it denied Hynix’s motion for reconsideration in February 2009.
The second phase dealt with Rambus’ allegations that Hynix memory products infringed its patents. In April 2006, a jury unanimously found that all 10 Rambus patent claims at issue in that trial are valid and infringed by Hynix memory products. The jury award of approximately $307 million in damages for US sales of infringing Hynix products through December 31, 2005, was subsequently reduced by the Court to approximately $134 million.
In the third and final phase of the case, Hynix (together with Micron and Nanya) tried its remaining claims and defenses against Rambus including antitrust and fraud claims based on Rambus’ participation in a standard-setting organization called JEDEC. In March 2008, a jury found Rambus had acted properly during its participation in JEDEC in the early 1990s. The Court similarly found in Rambus’ favor in a decision issued on March 3, 2009.
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