Cadence unveils integrated chip planning and implementation solution

USA:Cadence Design Systems Inc. today unveiled a breakthrough solution that provides design and implementation engineers with superior visibility and predictability of chip performance, area, power consumption, cost, and time to market across the full range of design activities, including system-level design and IP selection through final implementation and signoff.

This unique and automated approach to semiconductor design has been achieved through the integration of Cadence InCyte Chip Estimator and the Cadence Encounter Digital Implementation (EDI) System technologies. The combination of these technologies increases the predictability of key metrics from design specification through final implementation while reducing overall IC project risk.

“As development costs of complex SoCs continue to skyrocket, manufacturers in all sectors are looking for increased visibility into their design processes,” said Richard Wawrzyniak, senior ASIC/SoC analyst at Semico Research Corporation. “By integrating capabilities from these two products, Cadence addresses a growing industry need by offering a solution that provides a unique and timely window into the development of a SoC.”

Decisions made during the architectural planning stages of the design cycle largely determine the chip’s resulting size, power consumption, performance, and cost. During these early stages design teams can realize the biggest benefits by considering and quantifying a variety of architectural and IP options prior to final design, implementation and signoff.

Traditionally, however, semiconductor designers have been forced to use a manual or disconnected approach to make estimations and architectural choices without the benefit of flexibility, automation, accurate analysis, or tight links to implementation tools. This new Cadence solution eliminates guesswork and provides a new data-driven and holistic approach to the optimization of IP selection and integration through architecture, design, implementation and signoff.

Using the new Cadence solution, designers can quickly and accurately estimate die size, power and cost, including real-time IP and manufacturing process what-if analysis to ease IP selection and determine design architecture and feasibility.

As a milestone in Cadence’s open, multi-vendor approach to IP, the solution leverages the vast ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries contribute data to enable this accurate what-if analysis capability. Once system-level trade-offs and architecture are complete, designers can dynamically progress to the final implementation phase, leveraging estimates as a seed and driving to faster convergence.

Cadence’s EDI System completes the implementation and signoff of the design while monitoring and tracking aspects of block and full-chip progress, and also providing in-situ updates to actual die-size, power consumption, performance and cost with full transparency to all stakeholders. As optimizations in EDI System improve yield, size or power, users can immediately quantify those benefits in terms of the fully packaged chip cost.

“This new solution offers a unique new advantage to semiconductor design teams where all parties involved from system-level architects to chip implementation engineers can now make more informed and precise tradeoffs, including technical and economic metrics,” said Charlie Huang, senior vice president and chief strategy officer at Cadence. “It breaks down the barriers between both domains for a more transparent and predictive semiconductor development process. This cost-aware design philosophy is a new paradigm for design teams and addresses the critical market need of cost and risk reduction in IC designs.”

The new design solution will be demonstrated at the Design Automation Conference in San Francisco this July and be available later this year.

Cadence Encounter system used by Gennum’s Snowbush IP Group

SAN JOSE, USA: Cadence Design Systems Inc. announced that Gennum Corp.'s Snowbush IP Group utilized the Cadence Encounter Digital Implementation System to develop the industry’s first 45-nanometer SuperSpeed USB 3.0 PHY IP core.

Encounter was used for timing closure and layout on the digital portion of the PHY. Introduced in March, the new IP from Gennum’s Snowbush IP Group features an integrated USB 3.0 PHY and controller IP with a 5-gigabit per second (Gb/s) transfer rate in each direction. The Encounter Digital Implementation System helped Gennum’s Snowbush IP design team quickly target the digital portion of the PHY to advanced 45nm and 40nm process technologies at multiple foundries, further expanding its market potential.

“The high-speed timing constraints of the PCS layer of the new USB 3.0 PHY require the highly capable design methodology offered by Encounter,” said John Wilby, director of engineering-PHY, for the Snowbush IP Group at Gennum. “The move from a competitor’s design environment to the Cadence Encounter Digital Implementation System took just three months from installation to first-pass silicon success. Key benefits with Encounter include its native signoff quality timing closure and support for advanced DFM rules in deep submicron technologies. In combination with low-power signoff, we also gained improved productivity, a high quality of silicon and ultimately faster time to market.”

Wilby also noted that the fully integrated Encounter Digital Implementation System allowed Gennum to raise the bar on its design specifications and improve the competitive differentiation of its customizable family of IP cores through improved power savings and chip performance, reduced jitter, and optimized noise immunity.

The Encounter Digital Implementation System is a configurable and extensible high-performance, high-capacity, scalable design solution uniquely delivering flat and hierarchical design closure and signoff analysis, as well as low-power, advanced-node, and mixed-signal design solutions in a single integrated environment. The system also delivers interoperability with package, logic, and custom IC design. Cadence design-for-manufacturing (DFM) technologies are an integral part of the Encounter Digital Implementation System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.

“Gennum’s Snowbush IP Group has a strong track record of success, and we’re pleased to play an integral role in the development of its latest high-speed family of customizable IP cores,” said Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. “This project was a success on multiple levels, but most notably it demonstrated that a full front-to-back design solution can be installed, ramped and used to deliver state-of-the-art advanced-node, low-power designs in a fraction of the time of previous solutions, with first-pass silicon success, lower risk, and faster time to market as the reward.”

Cadence's Encounter and how it matches up to Synopsys' Galaxy!

Early December 2008, Cadence Design Systems launched the Cadence Encounter Digital Implementation System, said to be a configurable digital implementation platform that delivers an incredible scalability with complete support for parallel processing across the design flow. Will it change the fortunes of the struggling EDA industry? EDA industry stats for Q3-08 given at the end of this post!

My first thoughts immediately went to Synopsys' Galaxy Custom Designer solution. This is the industry’s first modern-era mixed-signal implementation solution. Is the Cadence Encounter an answer to Synopsys' Galaxy? This is worth a shot!

Obviously, why has Cadence released Encounter now? How will the Encounter take on Synopsys' Galaxy? I managed to engage Rahul Deokar, Product Marketing Director, Cadence, to find out more.

The Encounter Digital Implementation System is a next generation high-performance, high-capacity RTL-GDS-II design closure solution with the industry's first end-to-end parallel processing flow that enables all steps of the design flow to be multi-CPU enabled -- from floorplanning, placement, routing, extraction to timing and signal integrity sign-off. He said, "At its core is a new memory management architecture and end to end multi-CPU backplane that provides scalability with increased performance and capacity to reduce design time and time-to-market."

Does it intend to take on Synopsys' Galaxy? Well, Deokar said: "Yes, it surpasses the other solutions available in the marketplace based on the following capabilities and features, which are:
* Ultra-scalable RTL-to-GDS-II system with superior design closure and signoff analysis for low-power, mixed-signal, advanced node designs.
* End-to-end multi-core infrastructure and advanced memory architecture for unparalleled scalability of capacity, design turnaround time, and throughput.
* Robust design exploration and automated floorplan synthesis and ranking solution.
* Embedded signoff-qualified variation analysis and optimization across design flow.
* Integrated diagnostic tools for rapid global timing, clock and power analysis/debug

Here’s a list of benefits that it provides designers:
* Significantly reduces design time, schedule and development risk.
* Increased productivity through automation; superior quality of results.
* Configurable and extensible platform that ensures maximum utilization and ROI -- upgrades proven design flow and amplifies existing expertise.
* Interoperability across package, logic, custom IC design, and manufacturability.

Harnessing power of multicore computing
According to Cadence, it provides complete support for parallel processing across the design flow. Does this mean that designers can fully harness the power of multicore computing? It would also mean that today's EDA tools capable enough to meet the multi-core challenge.

Deokar added: "Yes, the end-to-end parallel processing flow is supported across the entire design flow and consequently. Also, designers can fully harness the power of multicore computing. Today's designers commonly have dual CPU or even quad CPU machines on their desktop. The Encounter Digital Implementation System allows the designers to leverage their multi-CPU hardware and gain significant TAT improvements on the design cycle time and overall development schedule."

The Encounter end-to-end multi-CPU backplane delivers ultra-scale performance gains up to 16X in key areas such as routing and timing closure. All steps of the design flow are multi-CPU enabled. For instance, on a production design, when the Encounter is run on four CPUs, the user can get a 3.2X performance boost across the entire, end-to-end design flow.

Encounter deployed by over 15 customers?
Designers are said to be reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices. By what factors, and against which other tool(s) has Encounter been rated?

Deokar said that the Encounter Digital Implementation System has been developed in close collaboration with over 15 customer partners who have extensively used, validated and now, deployed it.

"Customers are already seeing overall design cycles significantly shorted by 25-30 percent, which translates to multiple weeks or even months. These significant improvements are against competitive tool flows in their current methodology," he added.

Encounter is also said to be offering new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow.

Regarding this aspect, he pointed out that large scale design complexities (increased functionality, predictability, productivity, etc.,) pose some of the biggest challenges. Designs are getting huge at 100M+ gates, 100+ macros in the design, putting significant requirements on design tools, particularly, floorplanning of these macros, and the whole design becomes a huge challenge.

"The new Silicon Virtual Prototyping capabilities of Automated Floorplan Synthesis and Die Size Exploration help out exactly on that front. These can quickly provide floorplanning for that large 100M+ gates, 100+ macro design.

"And not just one floorplan, but designers can provide multiple criteria (say, along the lines of timing or power or area or congestion) and you will get multiple floorplans with their rankings…-- all this in a matter of minutes! Essentially, you could finish your breakfast or lunch (depending upon how fast you eat!) and be back to have multiple floorplans that you can then pick and choose from, and then proceed to implementation."

Addressing new problems at 45nm/40nm/32nm
Obviously, targeted at 45nm/40nm/32nm, etc., how can or how does Encounter anticipate and address the majority of the new problems associated with these geometries across the entire flow?

Deokar noted that its main customers include semiconductor companies working on 45nm and 32nm designs, with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content.

"The challenges facing these designs comprise of an increasing demand for design tool performance/capacity and design features for challenging ultra-large scale designs in the areas of low power, mixed signal, advanced node and signoff analysis. In addition, small market windows and product life-cycles and the cost pressures further exacerbate the situation," he noted.

The Encounter Digital Implementation System’s core design closure capabilities, plus the new advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization provide comprehensive manufacturing- and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure even on the most challenging designs.

Reducing memory footprints
It will be interesting to learn about the kind of work that has gone into reducing the memory footprint of the most memory-retentive applications.

Deokar said that an innovative memory architecture is at the core of the Encounter System that enables capacity and performance gains of 30-40 percent for full flat and hierarchical designs, even if you are running on a single-CPU machine.

Cadence's R&D team has developed an advanced memory defragmentation algorithm that allows the applications to be extremely memory-frugal …and that memory-efficiency enables designers to handle their biggest 100M+ instance designs.

Parallels with Synopsys' Galaxy Custom Designer?
There seem to be parallels with Synopsys' Galaxy Custom Designer for AMS. Also, there could be some chance of Cadence's Virtuoso and Encounter coming together in future.

According to Deokar, Synopsys’ Custom Designer for AMS is its entry into the full-custom/analog design marketplace, where the Cadence Virtuoso platform is a strong incumbent.

He said: "The biggest challenge for mixed signal designers is the efforts/resources involved in taking design data from the full-custom/analog tools to the digital implementation tools, and back and forth…in never-ending iterations.

"Now, with the Encounter Digital Implementation System, designers get the seamless full-custom/analog and digital design implementation interoperability…with unified constraints handling, mixed-signal floorplanning and ECO. It executes off a common design database (OpenAccess), enabling edits made in one design environment (e.g. Virtuoso) to be easily seen in the other design environment (e.g. Encounter). It also enables the design team to easily transfer the design data, to determine the optimal floorplan based on analog and digital constraints."

For example, the analog design team moves pins on the analog block, when the design is opened in Encounter, the modified pin locations are easily seen and the digital design team can execute a pin optimization to re-align the pins at the top-level.

In addition, the user can enter routing constraints in either Encounter or Virtuoso, and implement mixed signal routing in either environment. Top-level routing constraints could be defined within Virtuoso, then the top-level routing completed using the mixed signal routing functionality within Encounter.

Customers are already seeing their overall design schedules significantly reduced, added Deokar.

Postscript: Well, as expected, the EDA industry has taken a hit again. As per the EDA Consortium (EDAC) Market Statistics Service (MSS), the EDA industry revenue for Q3 2008 declined 10.9 percent to $1,258.6 million compared to $1,412.1 million in Q3 2007. The four-quarter moving average declined 2.8 percent.

Now, does Cadence's Encounter have the ability to turn around the EDA industry's fortunes? I don't think so! Much more needs to be done by Cadence and all of the other EDA companies!