EDA industry revenue down in Q2-09

SAN JOSE, USA: The EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the Electronic Design Automation (EDA) industry revenue for Q2 2009 is $1,125.5 million, a 5.6 percent sequential decline from Q1.

On a Q2/Q2 basis, EDA industry revenue declined 15.8 percent to $1,125.5 million, compared to $1,335.9 million in Q2 2008. The four-quarter moving average declined 13.9 percent.

“This recession started with the most precipitous drop in electronics industry history. Nevertheless, the normal pattern of preserving most R&D spending has been maintained by most electronics companies,” said Wally Rhines, EDAC chair and chairman and CEO of Mentor Graphics. “As the electronics industry recovers, and its R&D spending increases to come in line with its growing revenue, the EDA industry would be expected to recover as well.”

Companies that were tracked employed 26,298 professionals in Q2 2009, down 6.1 percent from the 28,004 employed in Q2 2008, and down 1.0 percent from the 26,561 employed in Q1 2009.

Revenue by product category
Computer Aided Engineering (CAE), EDA’s largest category, generated revenue of $449.7 million in Q2 2009. This represents a 12.2 percent decrease over the same period in 2008. The four-quarter moving average for CAE declined 18.6 percent.

In the next largest category, IC Physical Design and Verification, revenue decreased to $270.6 million in Q2 2009, a 12.8 percent decrease compared to Q2 2008. The four-quarter moving average declined 19.7 percent for IC Physical Design & Verification.

Printed Circuit Board and Multi-Chip Module (PCB and MCM) revenue decreased 24.1 percent compared to Q2 2008, to $105.8 million. The four-quarter moving average for PCB and MCM decreased 10.4 percent.

Semiconductor Intellectual Property (SIP) revenue totaled $221.6 million in Q2 2009, a 16.3 percent decrease compared to Q2 2008. The four-quarter moving average for SIP decreased 5.0 percent.

Services revenue was $77.8 million in Q2 2009, a decrease of 28.6 percent compared to Q2 2008. The four-quarter moving average for services increased 7.5 percent.

Revenue by consuming region
The Americas, EDA’s largest region, purchased $509 million of EDA products and services in Q2 2009, representing an 11.5 percent decrease compared to Q2 2008. The four-quarter moving average was down 14.7 percent for the region.

Revenue in Europe, the Middle East, and Africa (EMEA) was down 21.1 percent in Q2 2009 compared to Q2 2008 on revenues of $212.4 million. The four-quarter moving average for EMEA was down 14.3 percent.

Q2 2009 revenue from Japan decreased 21.5 percent to $217.8 million compared to Q2 2008. The four-quarter moving average for Japan decreased 17.9 percent.

The Asia/Pacific (APAC) region decreased to $186.3 million in Q2 2009, a 13.1 percent decrease compared to the same quarter in 2008. The four-quarter moving average declined 5.3 percent.

Global semicon mid-year review: Chip market revival or blip on stats radar screen?

A recent report from Future Horizons suggests an 18 percent growth for the chip market in Q2-2009! So, is this a sign of the chip market recovery or a mere blip on the statistics radar screen?

It is both, said, Malcolm Penn, chairman, founder and CEO of Future Horizons, and counselled that: "The fourth quarter market collapse was far too steep -- a severe over-reaction to last year's gross financial uncertainty -- culminating with the Lehman Brothers collapse in September. The first quarter saw this stabilise with the second quarter restocking, but there are other positive factors also in play."

Examining a bit further, here's what he further revealed. One, the memory market is seeing some signs of slow recovery. He said, "This has already started DDR3 driven!" Likewise, companies are also in the process of revising their forecasts. The reason, Penn contended, being, "The maths has changed dramatically since Jan 2009!"

According to him, factors now leading to conditions looking up in H2 2009, include the normal seasonal demand -- from a tight inventory base -- and tightening capacity. There is also a clear indication of the correction phase to rebalance over-depleted inventories having started. "This is what's driving Q2's high unit, and therefore, sales growth," he contended.

Firms advised to stop seeing and waiting!
This isn't all! Penn further counselled firms who are still in a wait-and-see mode to 'stop seeing and waiting'! Next, fabs are also looking to maximize their returns. For one, they have stopped over-investing.

Do we have enough stats from others to back up what's been happening in the global semiconductor industry? Perhaps, yes!

IC Insights stands out
First, look at IC Insights! It has stood out by pointing out in early July that H2-09 is likely to usher in strong seasonal strength for electronic system sales, a period of IC inventory replenishment, which began in 2Q09, and positive worldwide GDP growth.

IC Insights has predicted global IC market to grow +18 percent; IC foundry sales to grow +43 percent; and semiconductor capital spending to grow +28 percent in H2-09.

DDR3 driving memory recovery? Flat NAND?
Elsewhere, Converge Market Insights said that according to major DRAM manufacturers, DDR3 demand has been on the rise over the last two months and supply is limited.

This is quite in line with Future Horizons contention that there is a DDR3 driven memory recovery, albeit slow. It would be interesting to see how Q3-09 plays out.

As for NAND, according to DRAMeXchange, the NAND market may continue to show the tug-of-war status in July due to dissimilar positive and negative market factors perceived and expected by both sides. As a result, NAND Flash contract prices are likely to somewhat soften or stay flat in the short term.

Semicon equipment market to decline 52 percent in 2009!
According to SEMI, it projects 2009 semiconductor equipment sales to reach $14.14 billion as per the mid-year edition of the SEMI Capital Equipment Forecast, released by SEMI at the annual SEMICON West exposition.

The forecast indicates that, following a 31 percent market decline in 2008, the equipment market will decline another 52 percent in 2009, but will experience a rebound with annual growth of about 47 percent in 2010.

EDA cause for concern
The EDA industry still remains a cause for concern. The EDA Consortium's Market Statistics Service (MSS) announced that the EDA industry revenue for Q1 2009 declined 10.7 percent to $1,192.1 million, compared to $1,334.2 million in Q1 2008, driven primarily by an accounting shift at one major EDA company. The four-quarter moving average declined 11.3 percent.

If you look at the last five quarters, the EDA industry has really been having it rough. Here are the numbers over the last five quarters, as per the Consortium:

* The EDA industry revenue for Q1 2008 declined 1.2 percent to $1,350.7 million compared to $1,366.8 million in Q1 2007.
* The industry revenue for Q2 2008 declined 3.7 percent to $1,357.4 million compared to $1,408.8 million in Q2 2007.
* The industry revenue for Q3 2008 declined 10.9 percent to $1,258.6 million compared to $1,412.1 million in Q3 2007.
* The industry revenue for Q4 2008 declined 17.7 percent to $1,318.7 million, compared to $1,602.7 million in Q4 2007.

Therefore, at the end of the day, what do you have? For now, the early recovery signs are more of a blip on the stats radar screen and there's still some way to go and work to be done before the global semiconductor industry can clearly proclaim full recovery!

Before I close, a word about the Indian semiconductor industry. Perhaps, it needs to start moving a bit faster and quicker than it is doing presently. Borrowing a line from Malcolm Penn, the Indian semiconductor industry surely needs to "stop waiting and watching."

I will be in conversation next with iSuppli on the chip and electronics industry forecasts. Keep watching this space, friends.

EDA industry revenue down 10.7pc in Q1-09: EDA Consortium

SAN JOSE, USA: The EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the electronic design automation (EDA) industry revenue for Q1 2009 declined 10.7 percent to $1192.1 million, compared to $1334.2 million in Q1 2008, driven primarily by an accounting shift at one major EDA company. The four-quarter moving average declined 11.3 percent.

“The business environment remained difficult for EDA as for other industries, with Q1 EDA revenues declining in all regions except Asia Pacific,” said Walden C. Rhines, EDA Consortium chair and Mentor Graphics CEO and chairman. “Nevertheless, for Q1, the overall decline was less than for the previous quarter.”

Companies that were tracked employed 26,561 professionals in Q1 2009, down 2.8 percent from the 27,329 employed in Q1 2008, and down 2.7 percent from the 27,311 employed in Q4 2008.

Revenue by product category
Computer Aided Engineering (CAE), EDA’s largest category, generated revenue of $427.9 million in Q1 2009. This represents an 18.8 percent decrease over the same period in 2008. The four-quarter moving average for CAE declined 16.8 percent.

In the next largest category, IC Physical Design & Verification, revenue decreased to $302.2 million in Q1 2009, a 5.4 percent decrease compared to Q1 2008. The four-quarter moving average declined 21.6 percent for IC Physical Design & Verification.

Printed Circuit Board and Multi-Chip Module (PCB & MCM) revenue decreased 7.1 percent compared to Q1 2008, to $119.9 million. The four-quarter moving average for PCB & MCM decreased 0.6 percent.

Semiconductor Intellectual Property (SIP) revenue totaled $236.3 million in Q1 2009, a 12.8 percent decrease compared to Q1 2008. The four-quarter moving average for SIP decreased 1.4 percent.

Services revenue was $105.7 million in Q1 2009, an increase of 20.4 percent compared to Q1 2008. The four-quarter moving average for services was up 24.6 percent.

Revenue by Consuming Region
The Americas, EDA’s largest region, purchased $494 million of EDA products and services in Q1 2009, representing an 11.6 percent decrease compared to Q1 2008. The four-quarter moving average was down 15.4 percent for the region.

Europe, the Middle East, and Africa (EMEA) revenue was down 15.9 percent in Q1 2009 compared to Q1 2008, with revenues of $223.2 million. The four-quarter moving average for Western Europe was down 7.5 percent.

Q1 2009 revenue from Japan decreased 17.7 percent to $265.5 million compared to Q1 2008. The four-quarter moving average for Japan decreased 10.8 percent.

The Asia/Pacific (APAC) region increased to $209.4 million in Q1 2009, an 11.5 percent increase compared to the same quarter in 2008. The four-quarter moving average declined 4.7 percent.

EDA Consortium conducts multi-faceted investigation into EDA software piracy

SAN JOSE, USA: The EDA Consortium (EDAC) Anti-Piracy Committee is conducting an on-going investigation into EDA software piracy on multiple fronts.

“Until recently, many EDA vendors considered the software too complex to use without significant technical support for piracy to be a major concern. Advances in EDA software and access to fabrication have resulted in increasing concerns about software piracy” said Scott Baeder, Chairman of the EDA Consortium’s Anti-Piracy Committee and Senior Architect at Cadence Design Systems, Inc.

The EDA Consortium is working with multiple companies in the anti-piracy field to investigate EDA software piracy from multiple aspects. One aspect is availability – what software is available and where. Using a carefully chosen sampling of EDA products from various EDAC member companies, an investigation was conducted for EDAC by Arxan, Inc. into pirated EDA software availability and download activity on the internet. This will be followed by a more detailed investigation into how the “cracking” is being done, which could lead to improved software protection. Initial results have been interesting both from the standpoint of what is being pirated and the audacity of the pirates.

Another aspect of the investigation is focusing more on detection and identification of unauthorized use. A recent webinar conducted by V.i. Labs, Inc and EDAC presented this approach, which has been successfully used by EDAC members and others to re-coup revenues that would have been lost through piracy, both intentional and inadvertent. (Recognizing there are cases where the end user may not be aware they are using pirated software.)

A third aspect of the investigation, conducted for EDAC by S.A.F.E. Inc., bridges the other two approaches, looking at both the potential software vulnerabilities and the extent of the revenue loss to EDA vendors. This investigation looks at different categories of EDA software as well as different types of piracy, both intentional and unintentional.

In addition to the ongoing investigations, Mr. Baeder recently presented an overview of EDA software piracy to ICAF – Industrial College of the Armed Forces – which may have an interest in any national security implications of software piracy.

As the investigation proceeds, interim results have been presented to the EDAC Board of Directors and members. When the investigations are concluded, final reports will be made available to EDAC members.

Cadence's Encounter and how it matches up to Synopsys' Galaxy!

Early December 2008, Cadence Design Systems launched the Cadence Encounter Digital Implementation System, said to be a configurable digital implementation platform that delivers an incredible scalability with complete support for parallel processing across the design flow. Will it change the fortunes of the struggling EDA industry? EDA industry stats for Q3-08 given at the end of this post!

My first thoughts immediately went to Synopsys' Galaxy Custom Designer solution. This is the industry’s first modern-era mixed-signal implementation solution. Is the Cadence Encounter an answer to Synopsys' Galaxy? This is worth a shot!

Obviously, why has Cadence released Encounter now? How will the Encounter take on Synopsys' Galaxy? I managed to engage Rahul Deokar, Product Marketing Director, Cadence, to find out more.

The Encounter Digital Implementation System is a next generation high-performance, high-capacity RTL-GDS-II design closure solution with the industry's first end-to-end parallel processing flow that enables all steps of the design flow to be multi-CPU enabled -- from floorplanning, placement, routing, extraction to timing and signal integrity sign-off. He said, "At its core is a new memory management architecture and end to end multi-CPU backplane that provides scalability with increased performance and capacity to reduce design time and time-to-market."

Does it intend to take on Synopsys' Galaxy? Well, Deokar said: "Yes, it surpasses the other solutions available in the marketplace based on the following capabilities and features, which are:
* Ultra-scalable RTL-to-GDS-II system with superior design closure and signoff analysis for low-power, mixed-signal, advanced node designs.
* End-to-end multi-core infrastructure and advanced memory architecture for unparalleled scalability of capacity, design turnaround time, and throughput.
* Robust design exploration and automated floorplan synthesis and ranking solution.
* Embedded signoff-qualified variation analysis and optimization across design flow.
* Integrated diagnostic tools for rapid global timing, clock and power analysis/debug

Here’s a list of benefits that it provides designers:
* Significantly reduces design time, schedule and development risk.
* Increased productivity through automation; superior quality of results.
* Configurable and extensible platform that ensures maximum utilization and ROI -- upgrades proven design flow and amplifies existing expertise.
* Interoperability across package, logic, custom IC design, and manufacturability.

Harnessing power of multicore computing
According to Cadence, it provides complete support for parallel processing across the design flow. Does this mean that designers can fully harness the power of multicore computing? It would also mean that today's EDA tools capable enough to meet the multi-core challenge.

Deokar added: "Yes, the end-to-end parallel processing flow is supported across the entire design flow and consequently. Also, designers can fully harness the power of multicore computing. Today's designers commonly have dual CPU or even quad CPU machines on their desktop. The Encounter Digital Implementation System allows the designers to leverage their multi-CPU hardware and gain significant TAT improvements on the design cycle time and overall development schedule."

The Encounter end-to-end multi-CPU backplane delivers ultra-scale performance gains up to 16X in key areas such as routing and timing closure. All steps of the design flow are multi-CPU enabled. For instance, on a production design, when the Encounter is run on four CPUs, the user can get a 3.2X performance boost across the entire, end-to-end design flow.

Encounter deployed by over 15 customers?
Designers are said to be reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices. By what factors, and against which other tool(s) has Encounter been rated?

Deokar said that the Encounter Digital Implementation System has been developed in close collaboration with over 15 customer partners who have extensively used, validated and now, deployed it.

"Customers are already seeing overall design cycles significantly shorted by 25-30 percent, which translates to multiple weeks or even months. These significant improvements are against competitive tool flows in their current methodology," he added.

Encounter is also said to be offering new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow.

Regarding this aspect, he pointed out that large scale design complexities (increased functionality, predictability, productivity, etc.,) pose some of the biggest challenges. Designs are getting huge at 100M+ gates, 100+ macros in the design, putting significant requirements on design tools, particularly, floorplanning of these macros, and the whole design becomes a huge challenge.

"The new Silicon Virtual Prototyping capabilities of Automated Floorplan Synthesis and Die Size Exploration help out exactly on that front. These can quickly provide floorplanning for that large 100M+ gates, 100+ macro design.

"And not just one floorplan, but designers can provide multiple criteria (say, along the lines of timing or power or area or congestion) and you will get multiple floorplans with their rankings…-- all this in a matter of minutes! Essentially, you could finish your breakfast or lunch (depending upon how fast you eat!) and be back to have multiple floorplans that you can then pick and choose from, and then proceed to implementation."

Addressing new problems at 45nm/40nm/32nm
Obviously, targeted at 45nm/40nm/32nm, etc., how can or how does Encounter anticipate and address the majority of the new problems associated with these geometries across the entire flow?

Deokar noted that its main customers include semiconductor companies working on 45nm and 32nm designs, with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content.

"The challenges facing these designs comprise of an increasing demand for design tool performance/capacity and design features for challenging ultra-large scale designs in the areas of low power, mixed signal, advanced node and signoff analysis. In addition, small market windows and product life-cycles and the cost pressures further exacerbate the situation," he noted.

The Encounter Digital Implementation System’s core design closure capabilities, plus the new advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization provide comprehensive manufacturing- and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure even on the most challenging designs.

Reducing memory footprints
It will be interesting to learn about the kind of work that has gone into reducing the memory footprint of the most memory-retentive applications.

Deokar said that an innovative memory architecture is at the core of the Encounter System that enables capacity and performance gains of 30-40 percent for full flat and hierarchical designs, even if you are running on a single-CPU machine.

Cadence's R&D team has developed an advanced memory defragmentation algorithm that allows the applications to be extremely memory-frugal …and that memory-efficiency enables designers to handle their biggest 100M+ instance designs.

Parallels with Synopsys' Galaxy Custom Designer?
There seem to be parallels with Synopsys' Galaxy Custom Designer for AMS. Also, there could be some chance of Cadence's Virtuoso and Encounter coming together in future.

According to Deokar, Synopsys’ Custom Designer for AMS is its entry into the full-custom/analog design marketplace, where the Cadence Virtuoso platform is a strong incumbent.

He said: "The biggest challenge for mixed signal designers is the efforts/resources involved in taking design data from the full-custom/analog tools to the digital implementation tools, and back and forth…in never-ending iterations.

"Now, with the Encounter Digital Implementation System, designers get the seamless full-custom/analog and digital design implementation interoperability…with unified constraints handling, mixed-signal floorplanning and ECO. It executes off a common design database (OpenAccess), enabling edits made in one design environment (e.g. Virtuoso) to be easily seen in the other design environment (e.g. Encounter). It also enables the design team to easily transfer the design data, to determine the optimal floorplan based on analog and digital constraints."

For example, the analog design team moves pins on the analog block, when the design is opened in Encounter, the modified pin locations are easily seen and the digital design team can execute a pin optimization to re-align the pins at the top-level.

In addition, the user can enter routing constraints in either Encounter or Virtuoso, and implement mixed signal routing in either environment. Top-level routing constraints could be defined within Virtuoso, then the top-level routing completed using the mixed signal routing functionality within Encounter.

Customers are already seeing their overall design schedules significantly reduced, added Deokar.

Postscript: Well, as expected, the EDA industry has taken a hit again. As per the EDA Consortium (EDAC) Market Statistics Service (MSS), the EDA industry revenue for Q3 2008 declined 10.9 percent to $1,258.6 million compared to $1,412.1 million in Q3 2007. The four-quarter moving average declined 2.8 percent.

Now, does Cadence's Encounter have the ability to turn around the EDA industry's fortunes? I don't think so! Much more needs to be done by Cadence and all of the other EDA companies!