SAN JOSE, USA: Silicon & Software Ltd. (S3), a worldwide leading provider of design services, consultancy and software products to the semiconductor industry, the digital TV industry and the telehealth industry, has joined the Power Forward Initiative (PFI).
Established by Cadence Design Systems Inc. and its partners to develop comprehensive approaches to power-efficient design, PFI now welcomes S3 as the organization continues to advance low power standards and solutions.
S3 has been focused on low power design for over 20 years, and has a heritage of contributing to power standards for wireless design, from the Digital Enhanced Cordless Telecommunications (DECT) standard to the Long Term Evolution (LTE) standard for radio technologies.
The company has full analog-digital-RF SoC architecture, design and verification capabilities. S3 has also developed advanced low power methodologies to automate design techniques such as voltage islands and voltage gating in nanometer nodes, which it has been applying since 2004.
Recently, S3 integrated the Common Power Format (CPF) into its proprietary NanoFlow environment, thereby reducing risk and accelerating time to market for low power designs. S3’s design services expertise is complemented by an extensive portfolio of silicon-proven power management products including Mixed Signal IP (DC/DC, Linear Regulators, and Power Switches).
“We are happy to bring our low power implementation knowledge, and experience, including multiple tapeouts at leading edge geometries, to help address the common goals of the PFI. We are looking forward to making what we hope will be valuable contributions to the initiative,” said James Blair, Director of Consumer Silicon Services, S3.
“It is a pleasure to welcome S3, with such a strong legacy in the IC design industry, into the Power Forward Initiative,” said Steve Carlson, vice president of Low Power Solutions marketing at Cadence. “With the addition of S3 the Power Forward Initiative has grown to over 40 highly reputable members, all of whom are delivering on our common goal of bringing high-quality, low power methodologies, solutions, services and silicon to customers globally.”
Showing posts with label CPF. Show all posts
Showing posts with label CPF. Show all posts
Friday, 2 October 2009
Monday, 20 July 2009
Sequence's PowerArtist-XP -- first automatic, fully integrated RTL design for power platform
SUNNYVALE, USA: Sequence Design has announced PowerArtist-XP, the first and most comprehensive analysis-driven, automatic RTL power-reduction technology within a completely integrated environment.
IP and SoC RTL designers, without becoming power experts, can analyze, visualize and reduce power by 10-60 percent or more within minutes on multi-million instances, with 50 percent fewer RTL edits, and productivity gains of 10X at a minimum.
“Power management is a top priority and Sequence’s PowerArtist-XP is a key tool we use for power efficient RTL design flows,” said Jiebing Wang, Vice President of Acceleration Technology at Exar Corp.
“The tool has provided significant power reduction in our designs. PowerArtist-XP also has enabled our RTL designers to become power aware by providing methods to analyze and reduce power early in the design process while being easy to integrate in our design flows.”
PowerArtist-XP -– selected as a DAC 2009 “must-see” by famed analyst Gary Smith – will be showcased alongside Sequence’s complete technology lineup at this year’s DAC, Booth 3455.
The tool delivers maximum power savings, in minimum time, with the least number of RTL edits. Sequence’s new XPRT (eXtreme Power Reduction Technology) incorporated here maximizes power savings early at RTL -– the highest level of hardware abstraction enabling high productivity.
XPRT delivers the industry’s most comprehensive set of RTL power reductions yet – power reduction is not just sequential and combinational clock gating, but is also targeted for memory and datapath portions of complex SoCs and IPs.
Integrating the industry-leading PowerTheater timing-aware power analysis technology, PowerArtist-XP users now benefit from a one-stop shop for RTL power. By predicting power savings and area trade-offs upfront at RTL, single-pass power reduction identifies the highest impact RTL edits.
Productivity increases multi-fold by obviating unnecessary iterations with synthesis and implementation while decreasing the impact on area, timing closure, verification, and functional ECOs. The integrated RTL power environment also enables designers to quickly discover power bugs, manage stimulus for peak and average power, generate custom reports for power regressions using the OpenAccess database, and more.
A powerful graphical cockpit, PowerCanvas, drives power-ordered reductions while providing a wide range of tightly interlinked visual debug diagnostics that make power easy for mainstream RTL designers.
PowerArtist-XP automatically generates power-optimized RTL with surgical changes -– in addition, the versatile PowerCanvas reduction dialogs provide both flexibility and precise guidance to the RTL designers in making rapid RTL edits.
“PowerArtist has proven itself by giving us the power savings and productivity gains we need,” said Jon Gibbons, Ubicom Vice President of VLSI Engineering. “By raising the bar with PowerArtist-XP, Sequence continues to advance the state of the art in low-power design, and we look forward to working with this exciting new technology.”
“Since we launched PowerArtist at DAC last year, we saw a growing demand from customers for an integrated solution addressing power reduction more intelligently,” said Vic Kulkarni, President & CEO of Sequence.
“For sub-65nm designs, an RTL analysis-driven power reduction approach becomes very critical since surgical changes are now possible in order to achieve maximum possible power reduction with minimal area overhead and minimal ECO loops. Power reduction with analysis-driven vs. ‘blind’ automation is the only meaningful approach for designers to lower power and avoid falling in the traps of poor QoR and an excess of ineffective changes.”
PowerArtist-XP is compatible with all standard design flows, including synthesis, simulation, and formal verification, and all leading formats and constraints including Common Power Format (CPF), Unified Power Format (UPF) and Synopsys Design Constraints (SDC).
Utilizing Si2’s OpenAccess database (OADB), it uniquely allows users to have detailed access to power information to create custom reports or automate proprietary power reductions through an open Tcl API.
PowerArtist-XP is in production now. North America list pricing starts at $220,000 for a one-year TBL.
IP and SoC RTL designers, without becoming power experts, can analyze, visualize and reduce power by 10-60 percent or more within minutes on multi-million instances, with 50 percent fewer RTL edits, and productivity gains of 10X at a minimum.
“Power management is a top priority and Sequence’s PowerArtist-XP is a key tool we use for power efficient RTL design flows,” said Jiebing Wang, Vice President of Acceleration Technology at Exar Corp.
“The tool has provided significant power reduction in our designs. PowerArtist-XP also has enabled our RTL designers to become power aware by providing methods to analyze and reduce power early in the design process while being easy to integrate in our design flows.”
PowerArtist-XP -– selected as a DAC 2009 “must-see” by famed analyst Gary Smith – will be showcased alongside Sequence’s complete technology lineup at this year’s DAC, Booth 3455.
The tool delivers maximum power savings, in minimum time, with the least number of RTL edits. Sequence’s new XPRT (eXtreme Power Reduction Technology) incorporated here maximizes power savings early at RTL -– the highest level of hardware abstraction enabling high productivity.
XPRT delivers the industry’s most comprehensive set of RTL power reductions yet – power reduction is not just sequential and combinational clock gating, but is also targeted for memory and datapath portions of complex SoCs and IPs.
Integrating the industry-leading PowerTheater timing-aware power analysis technology, PowerArtist-XP users now benefit from a one-stop shop for RTL power. By predicting power savings and area trade-offs upfront at RTL, single-pass power reduction identifies the highest impact RTL edits.
Productivity increases multi-fold by obviating unnecessary iterations with synthesis and implementation while decreasing the impact on area, timing closure, verification, and functional ECOs. The integrated RTL power environment also enables designers to quickly discover power bugs, manage stimulus for peak and average power, generate custom reports for power regressions using the OpenAccess database, and more.
A powerful graphical cockpit, PowerCanvas, drives power-ordered reductions while providing a wide range of tightly interlinked visual debug diagnostics that make power easy for mainstream RTL designers.
PowerArtist-XP automatically generates power-optimized RTL with surgical changes -– in addition, the versatile PowerCanvas reduction dialogs provide both flexibility and precise guidance to the RTL designers in making rapid RTL edits.
“PowerArtist has proven itself by giving us the power savings and productivity gains we need,” said Jon Gibbons, Ubicom Vice President of VLSI Engineering. “By raising the bar with PowerArtist-XP, Sequence continues to advance the state of the art in low-power design, and we look forward to working with this exciting new technology.”
“Since we launched PowerArtist at DAC last year, we saw a growing demand from customers for an integrated solution addressing power reduction more intelligently,” said Vic Kulkarni, President & CEO of Sequence.
“For sub-65nm designs, an RTL analysis-driven power reduction approach becomes very critical since surgical changes are now possible in order to achieve maximum possible power reduction with minimal area overhead and minimal ECO loops. Power reduction with analysis-driven vs. ‘blind’ automation is the only meaningful approach for designers to lower power and avoid falling in the traps of poor QoR and an excess of ineffective changes.”
PowerArtist-XP is compatible with all standard design flows, including synthesis, simulation, and formal verification, and all leading formats and constraints including Common Power Format (CPF), Unified Power Format (UPF) and Synopsys Design Constraints (SDC).
Utilizing Si2’s OpenAccess database (OADB), it uniquely allows users to have detailed access to power information to create custom reports or automate proprietary power reductions through an open Tcl API.
PowerArtist-XP is in production now. North America list pricing starts at $220,000 for a one-year TBL.
Friday, 10 July 2009
Si2 announces member demos at DAC 2009
Design Automation Conference 2009, AUSTIN, USA: Seven companies/organizations will be demonstrating significant progress advancing design flow interoperability in the Silicon Integration Initiative (Si2) Booth #1400 at the Design Automation Conference on July 26-31, at the Moscone Convention Center in San Francisco, CA.
These companies will be showing how Si2 standards such as OpenAccess, the Common Power Format (CPF), the Open Modeling Interface and new Design for Manufacturability techniques can provide innovative approaches to critical IC design flow issues.
The Design for Manufacturability demos will feature the top four EDA companies, two large IDMs, two startups and one research consortium that represents seven large Japanese companies and three Japanese Universities -– all working together!
AnaGlobe Technology: will demonstrate their OpenAccess-based integrated solution, customizable framework, supporting three scripting languages: TCL, Perl, and Python. Its second generation constraint-based OA Pcell Designer provides more powerful functions with a more friendly user interface which supports mixed use of TCL, Perl, and Python, and GUI.
Cadence Design Systems: will demonstrate solutions using several widely-deployed Si2 standards -- OpenAccess, Common Power Format, and ECSM. Hear from experts how you can use these industry-leading solutions from Cadence to address your most challenging mixed-signal, low-power, or advanced-node design problems.
Design for Manufacturability Coalition: will show two demos in the Si2 booth, supported by nine companies, including leading EDA vendors, large IDMs, startups and a research organization.
These demos will show: (1) Cell Level Find and Fix Demo that analyzes and corrects the DFM hotspots inside of approximately 100 different standard Open Cells; (2) Block Level Find and Fix Demo that analyzes and corrects the DFM hotspots in the routing between Open Cells with a ~100K+ gates (50K instances) Block. These demos will detail the standards that are in development that were used such as: Standard DRC checking, Standard Litho checking, Generic Litho Models, and Hotspot Interface Format
Magma Design Automation: will provide an overview of the Talus low-power design flow which provides the “Fastest Path to Silicon.” The Talus implementation system has enabled designers to meet the low-power specifications of some of the world’s most advanced handheld devices.
With support for the Common Power Format (CPF) and a unified datamodel architecture, Talus allows designers to implement advanced low-power design techniques throughout the flow and to significantly reduce turnaround time.
Pyxis Technology: will demonstrate the power of OpenAccess Interoperability through a seamless integration of the NexusRoute-HPC router with the Laker Custom Layout Automation System from SpringSoft. The demonstration will highlight the ability of the router and editor to simultaneously work off the same OpenAccess in-memory runtime model, a first for the EDA industry! Pyxis will be demonstrating Monday through Wednesday each morning from 9:00AM to 12:00 at the Si2 booth.
Open Modeling Coalition: will demonstrate the Open Model Interface (OMI) integrated with a third party timer, IBM's EinsTimer. The OMI enables a consistent view and use of various models across applications, thus allowing tools in multi-vendor design flows to better correlate with each other.
The interface leverages the Open Access API and data model and is extensible to allow for a variety of design models such as Liberty, ECSM and statistical ECSM among others.
The Si2 booth demonstration will use the OMI to connect the EinsTimer timing application with timing models using Liberty, ECSM and IEEE 1481 DPCM formats, separately and within the same timing run.
The Coalition will also demonstrate a multi-vendor standard cell library characterization and validation flow. The library being characterized is the Nangate Open library available on the Si2 website at http://www.si2.org/openeda.si2.org/projects/nangatelib/. Examples of the steps in the characterization process by Nangate, Altos, and Fenix will be shown in the booth.
Also being shown will be examples of characterization setup information that can be included in Liberty files and will lead to more standard characterization setups for any library characterization, validation, and model verification flow.
Synopsys: will demonstrate Galaxy Custom Designer: Built from the ground up on OpenAccess, Custom Designer was architected for productivity. This demonstration will show how our comprehensive solution addresses every step of the AMS IC implementation flow.
Productivity innovations in the schematic editor, simulation and analysis environment and schematic driven layout applications will be highlighted throughout the demo. You will also see how Custom Designer's optimized integration with IC Compiler, HSPICE, CustomSim, WaveView Analyzer, Hercules DRC/LVS and Star-RCXT parasitic extraction provides a productive solution all on the industry's most open environment.
These companies will be showing how Si2 standards such as OpenAccess, the Common Power Format (CPF), the Open Modeling Interface and new Design for Manufacturability techniques can provide innovative approaches to critical IC design flow issues.
The Design for Manufacturability demos will feature the top four EDA companies, two large IDMs, two startups and one research consortium that represents seven large Japanese companies and three Japanese Universities -– all working together!
AnaGlobe Technology: will demonstrate their OpenAccess-based integrated solution, customizable framework, supporting three scripting languages: TCL, Perl, and Python. Its second generation constraint-based OA Pcell Designer provides more powerful functions with a more friendly user interface which supports mixed use of TCL, Perl, and Python, and GUI.
Cadence Design Systems: will demonstrate solutions using several widely-deployed Si2 standards -- OpenAccess, Common Power Format, and ECSM. Hear from experts how you can use these industry-leading solutions from Cadence to address your most challenging mixed-signal, low-power, or advanced-node design problems.
Design for Manufacturability Coalition: will show two demos in the Si2 booth, supported by nine companies, including leading EDA vendors, large IDMs, startups and a research organization.
These demos will show: (1) Cell Level Find and Fix Demo that analyzes and corrects the DFM hotspots inside of approximately 100 different standard Open Cells; (2) Block Level Find and Fix Demo that analyzes and corrects the DFM hotspots in the routing between Open Cells with a ~100K+ gates (50K instances) Block. These demos will detail the standards that are in development that were used such as: Standard DRC checking, Standard Litho checking, Generic Litho Models, and Hotspot Interface Format
Magma Design Automation: will provide an overview of the Talus low-power design flow which provides the “Fastest Path to Silicon.” The Talus implementation system has enabled designers to meet the low-power specifications of some of the world’s most advanced handheld devices.
With support for the Common Power Format (CPF) and a unified datamodel architecture, Talus allows designers to implement advanced low-power design techniques throughout the flow and to significantly reduce turnaround time.
Pyxis Technology: will demonstrate the power of OpenAccess Interoperability through a seamless integration of the NexusRoute-HPC router with the Laker Custom Layout Automation System from SpringSoft. The demonstration will highlight the ability of the router and editor to simultaneously work off the same OpenAccess in-memory runtime model, a first for the EDA industry! Pyxis will be demonstrating Monday through Wednesday each morning from 9:00AM to 12:00 at the Si2 booth.
Open Modeling Coalition: will demonstrate the Open Model Interface (OMI) integrated with a third party timer, IBM's EinsTimer. The OMI enables a consistent view and use of various models across applications, thus allowing tools in multi-vendor design flows to better correlate with each other.
The interface leverages the Open Access API and data model and is extensible to allow for a variety of design models such as Liberty, ECSM and statistical ECSM among others.
The Si2 booth demonstration will use the OMI to connect the EinsTimer timing application with timing models using Liberty, ECSM and IEEE 1481 DPCM formats, separately and within the same timing run.
The Coalition will also demonstrate a multi-vendor standard cell library characterization and validation flow. The library being characterized is the Nangate Open library available on the Si2 website at http://www.si2.org/openeda.si2.org/projects/nangatelib/. Examples of the steps in the characterization process by Nangate, Altos, and Fenix will be shown in the booth.
Also being shown will be examples of characterization setup information that can be included in Liberty files and will lead to more standard characterization setups for any library characterization, validation, and model verification flow.
Synopsys: will demonstrate Galaxy Custom Designer: Built from the ground up on OpenAccess, Custom Designer was architected for productivity. This demonstration will show how our comprehensive solution addresses every step of the AMS IC implementation flow.
Productivity innovations in the schematic editor, simulation and analysis environment and schematic driven layout applications will be highlighted throughout the demo. You will also see how Custom Designer's optimized integration with IC Compiler, HSPICE, CustomSim, WaveView Analyzer, Hercules DRC/LVS and Star-RCXT parasitic extraction provides a productive solution all on the industry's most open environment.
Tuesday, 23 June 2009
Si2 to host low power coalition workshop at DAC 2009
AUSTIN, USA: The Silicon Integration Initiative (Si2) announced the Low Power Coalition workshop being hosted at the Design Automation Conference (DAC) show to be held at the Moscone Convention Center in San Francisco, CA, from July 26-31, 2009.
The “Low Power Coalition Workshop – Advances in Low Power Design throughout the design flow” will be held on July 26, from 1PM – 4:30PM in Room 130 in the Moscone Convention Center. In consideration of today’s economic conditions, Si2 is pleased to offer this workshop free of charge. Attendees can register at the DAC website: http://www.dac.com/46th/onlinereg.html
The Low Power Coalition (LPC) of Si2 has defined and published a power-aware reference flow that is recommended to the industry, including the power closure points and information available throughout the flow, from Electronic System Level (ESL) through implementation. This flow will be discussed.
To aid in automating many of the steps along the tool chain, a draft power intent data model and associated Application Procedural Interface (API) are being defined that will work seamlessly with the OpenAccess API and information model, and we will provide an early view of this data model and API.
In addition, enhancements have been made to extend the Common Power Format (CPF), an Si2 standard first released as v1.0 in March 2007 and v1.1 in September, 2008. The current status and future direction of the format will be presented, including progress since the last Low Power Workshop at DAC 2008, goals and plans for interoperability with P1801, and end-user experiences with the technology developed and implemented so far.
A panel will discuss “What’s Next,” to discuss areas in which power flows, models, and formats might be extended to support additional power-aware design approaches, such as adaptive methods, asynchronous methods, etc. A selection of advanced tools that have been developed by some of the EDA companies to improve power-aware design will also be presented.
Program
Introduction to the Low Power Coalition:
Gill Watt, AMD – Chairman of the LPC
Low Power Design Interoperability Requirements: Looking Ahead!
Qi Wang, Cadence, Vice Chair of the LPC Technical Steering Group
LPC Modeling Requirements for a Low Power Flow
Jerry Frenkil, Sequence, Member, LPC Modeling Working Group
LPC Data Model and API
Judith Richardson, AMD, Member, Data Model and API WG
End-user Adoption Aids
Jake Buurma, Si2
EDA Tool Developers for Low Power
Steve Carlson, Cadence Design Systems
Jerry Frenkil, Sequence Design, Inc.
Kiran Vittal, Atrenta, Inc.
Anmol Mathur, Calypto Design Systems, Inc.
Panel Discussion (all presenters)
“What’s next in Low Power”
The “Low Power Coalition Workshop – Advances in Low Power Design throughout the design flow” will be held on July 26, from 1PM – 4:30PM in Room 130 in the Moscone Convention Center. In consideration of today’s economic conditions, Si2 is pleased to offer this workshop free of charge. Attendees can register at the DAC website: http://www.dac.com/46th/onlinereg.html
The Low Power Coalition (LPC) of Si2 has defined and published a power-aware reference flow that is recommended to the industry, including the power closure points and information available throughout the flow, from Electronic System Level (ESL) through implementation. This flow will be discussed.
To aid in automating many of the steps along the tool chain, a draft power intent data model and associated Application Procedural Interface (API) are being defined that will work seamlessly with the OpenAccess API and information model, and we will provide an early view of this data model and API.
In addition, enhancements have been made to extend the Common Power Format (CPF), an Si2 standard first released as v1.0 in March 2007 and v1.1 in September, 2008. The current status and future direction of the format will be presented, including progress since the last Low Power Workshop at DAC 2008, goals and plans for interoperability with P1801, and end-user experiences with the technology developed and implemented so far.
A panel will discuss “What’s Next,” to discuss areas in which power flows, models, and formats might be extended to support additional power-aware design approaches, such as adaptive methods, asynchronous methods, etc. A selection of advanced tools that have been developed by some of the EDA companies to improve power-aware design will also be presented.
Program
Introduction to the Low Power Coalition:
Gill Watt, AMD – Chairman of the LPC
Low Power Design Interoperability Requirements: Looking Ahead!
Qi Wang, Cadence, Vice Chair of the LPC Technical Steering Group
LPC Modeling Requirements for a Low Power Flow
Jerry Frenkil, Sequence, Member, LPC Modeling Working Group
LPC Data Model and API
Judith Richardson, AMD, Member, Data Model and API WG
End-user Adoption Aids
Jake Buurma, Si2
EDA Tool Developers for Low Power
Steve Carlson, Cadence Design Systems
Jerry Frenkil, Sequence Design, Inc.
Kiran Vittal, Atrenta, Inc.
Anmol Mathur, Calypto Design Systems, Inc.
Panel Discussion (all presenters)
“What’s next in Low Power”
Wednesday, 18 June 2008
EDA as DNA of growth
The EDA industry today is abuzz with the proposed takeover bid by Cadence Design Systems for Mentor Graphics, and the reported rejection of that bid by Mentor.
This is a consolidation within the EDA industry waiting to happen. My gut feeling is that it will happen, though it may take some more time.
Those in the semiconductor space are well aware of the role EDA plays as far as chip designing is concerned. With India's growing might in semiconductors, the EDA companies in India are witnessing consumption rising than ever before.
I recently happened to get into a discussion with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd, on how the industry has been performing, and how are the EDA companies addressing the design challenges, a few days before the Cadence-Mentor story surfaced.
Following the semiconductor industry trends, the consumption of EDA technologies is growing in regions outside of the US and Europe. According to Arya, the size of the EDA market worldwide is estimated to be about US $5 billion today.
The top three EDA companies -- Cadence, Mentor and Synopsys -- command three-quarters share of the entire EDA market worldwide. Imagine, what it would do to the EDA industry and to Cadence, if Cadence were to take over Mentor!
EDA in India
Coming to the status of the EDA industry in India, it is a pretty good reflection of what's happening worldwide. The industry in India is growing and it is healthy. As per the ISA F&S Report 2005, the EDA market in India was estimated at US$110m.
The reasons for this growth are multiple. For instance, Cadence's customers are growing and hence, so is Cadence. "With all of the major semiconductor MNCs having expanded their footprints by setting up India design centers, more EDA software is getting consumed in India. Indian design services are also growing. Also, some startups are coming up, like Cosmic Circuits, Sankalp, etc., and they are gaining momentum," added Arya.
So how exactly are the EDA companies addressing 45nm (and 32nm) design challenges? If you look at the work being done in India, it is now pretty cutting edge, and very comparable to the rest of the world.
Arya added: "Our customers are looking for the 3Cs -- complexity, cost and convergence. The end users are asking for more features. For example, in their mobile or any other electronic device, which is driving our customers to pack in more functionality on the chips.
"Our customers have multiple challenges at 45nm and below, notably low power, analog-mixed signal and Design for Manufacturing (DFM)."
Challenges in 45nm and below
And what are those? As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to an increased risk and cost.
Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative (PFI).
Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP re-use.
The PFI members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.
Arya noted: "By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most —- innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.
On the subject of DFM, EDA companies are trying their utmost to improve yield. Cadence is trying to bring lot of analysis early in the cycle. The designer has more visibility on those effects, before they get manufactured. It has a host of technology offerings to enable the designers make early decisions.
For example, Cadence has recently worked with TSMC on 9.0 reference flow. It has also worked with ARM on a low-power methodology. The idea is that an industry-wide collaboration will ensure that EDA companies like Cadence are able to provide value to customers.
As customers grapple with technology and time-to-market challenges, the EDA industry will be the DNA of growth.
This is a consolidation within the EDA industry waiting to happen. My gut feeling is that it will happen, though it may take some more time.
Those in the semiconductor space are well aware of the role EDA plays as far as chip designing is concerned. With India's growing might in semiconductors, the EDA companies in India are witnessing consumption rising than ever before.
I recently happened to get into a discussion with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd, on how the industry has been performing, and how are the EDA companies addressing the design challenges, a few days before the Cadence-Mentor story surfaced.
Following the semiconductor industry trends, the consumption of EDA technologies is growing in regions outside of the US and Europe. According to Arya, the size of the EDA market worldwide is estimated to be about US $5 billion today.
The top three EDA companies -- Cadence, Mentor and Synopsys -- command three-quarters share of the entire EDA market worldwide. Imagine, what it would do to the EDA industry and to Cadence, if Cadence were to take over Mentor!
EDA in India
Coming to the status of the EDA industry in India, it is a pretty good reflection of what's happening worldwide. The industry in India is growing and it is healthy. As per the ISA F&S Report 2005, the EDA market in India was estimated at US$110m.
The reasons for this growth are multiple. For instance, Cadence's customers are growing and hence, so is Cadence. "With all of the major semiconductor MNCs having expanded their footprints by setting up India design centers, more EDA software is getting consumed in India. Indian design services are also growing. Also, some startups are coming up, like Cosmic Circuits, Sankalp, etc., and they are gaining momentum," added Arya.
So how exactly are the EDA companies addressing 45nm (and 32nm) design challenges? If you look at the work being done in India, it is now pretty cutting edge, and very comparable to the rest of the world.
Arya added: "Our customers are looking for the 3Cs -- complexity, cost and convergence. The end users are asking for more features. For example, in their mobile or any other electronic device, which is driving our customers to pack in more functionality on the chips.
"Our customers have multiple challenges at 45nm and below, notably low power, analog-mixed signal and Design for Manufacturing (DFM)."
Challenges in 45nm and below
And what are those? As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to an increased risk and cost.
Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative (PFI).
Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP re-use.
The PFI members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.
Arya noted: "By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most —- innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.
On the subject of DFM, EDA companies are trying their utmost to improve yield. Cadence is trying to bring lot of analysis early in the cycle. The designer has more visibility on those effects, before they get manufactured. It has a host of technology offerings to enable the designers make early decisions.
For example, Cadence has recently worked with TSMC on 9.0 reference flow. It has also worked with ARM on a low-power methodology. The idea is that an industry-wide collaboration will ensure that EDA companies like Cadence are able to provide value to customers.
As customers grapple with technology and time-to-market challenges, the EDA industry will be the DNA of growth.
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