CROLLES, FRANCE: STMicroelectronics and CEA-LETI, the French Laboratory for Electronics & Information Technology, have announced that Madame Christine Lagarde, the French Minister of Economy, Industry and Employment, along with representatives from national, regional and local authorities and managers from CEA-LETI and ST met at ST's site at Crolles, near Grenoble, France, to celebrate the formal launch of the Nano2012 Research and Development program.
Also present at the ceremony were representatives of IBM, which is a key partner of ST and CEA-LETI via important technology development agreements it has signed with both organizations.
Nano2012 is a public/private strategic R&D program, led by ST, which gathers research institutes and industrial partners and is supported by French national, regional and local authorities. The program aims to create one of the world's most advanced R&D clusters for the development of new generations of semiconductor technologies at the nanoelectronic level, where the dimensions of the structures used to build the silicon chips are in the order of tens of nanometers (billionths of a meter).
The Nano2012 co-operation program, along with other leading cooperative programs such as CATRENE, will significantly contribute to the continued strength of Europe's electronics industry by providing competitive access to the most advanced CMOS technologies from 32nm down to 22nm.
Work on the Nano2012 program started on January 1, 2008. The five-year program, which will run until December 31, 2012, is partly funded (Euros 457 million) by the French public authorities.
The program includes the participation of other partners such as INRIA (the French National Institute for Research in Computer Science and Control), CNRS (National Center for Scientific Research), universities, and many small- and medium-sized enterprise partners.
ST and CEA-LETI have a long history of R&D collaboration, including the initial set up of the Crolles R&D center in 1992. As a leading research laboratory, CEA-LETI provides a vital interface between long-term academic research and ST's market-driven industrial R&D.
In July 2007, ST joined the semiconductor Joint Development Alliance centered at IBM's Semiconductor Research and Development Center in East Fishkill and Albany, New York, which develops core and low-power CMOS processes from 32 to 22nm, and IBM joined ST in Crolles to develop value-added application-specific derivative CMOS technologies.
Additionally, CEA-LETI and IBM, which have strong and complementary expertise in the development of materials and processes required for CMOS technology, are collaborating on advanced process R&D down to 22nm and beyond, at CEA-LETI's Grenoble site (France), IBM's East Fishkill facility (NY), ST's Crolles site (France), and at the Albany NanoTech research center (NY).
Since the start of the Nano2012 program in January 2008, ST and IBM have exchanged researchers between their sites at Crolles and East Fishkill and have begun working along with researchers from CEA-LETI on a variety of key programs, including 32nm and 28 nm core CMOS processes, 45nm RF derivative technology for wireless applications and 65nm non-volatile-memory derivative technology for use in automotive and smart-card applications.
These technologies will allow exciting new products in communication, consumer, computer and automotive applications that consume less power and last longer on batteries, operate faster, and provide more functions and greater utility to end users.
Nano2012 focuses on technology platform development for low-power and application-specific derivative CMOS technologies. A technology platform encompasses the manufacturing process by which billions of transistors are integrated onto a single silicon chip as well as the components libraries and the design methodology to efficiently design leading-edge circuits in this process.
Utilizing its world-class teams based in Crolles and Grenoble, ST and its partners are already among the world leaders in this area and a key aim of Nano2012 is to extend this leadership.
Value-added application-specific derivative technologies are key differentiators to the standard CMOS technology and an important goal of Nano2012 is for the R&D cluster based in Grenoble-Isere to continue as a world leader in this field.
Showing posts with label CEA-Leti. Show all posts
Showing posts with label CEA-Leti. Show all posts
Saturday, 18 July 2009
Wednesday, 15 July 2009
Satin IP, Toppan Photomasks, XYALIS to improve DFMM
MONTPELLIER, ROUSSET & GRENOBLE, FRANCE: Satin IP Technologies SAS, Toppan Photomasks France SAS and XYALIS SaRL have collaborated within the Crystal partnership program to significantly improve design for mask manufacturing (DFMM) by breaking the barriers that have traditionally separated integrated chip (IC) designers from mask shop engineers.
Crystal is a European collaborative R&D program sponsored by the Cluster for Application and Technology Research in Europe on NanoElectronics (CATRENE). Other participants include Atmel and CEA-LETI.
While the old design rule checkers (DRC) developed into sophisticated and pro-active design for manufacturing (DFM) tool suites, the mask rules checks are still implemented at the final phase when the GDSII data is released.
Resolution enhancement techniques (RET) and optical proximity correction (OPC) further restrict the ability to revise the design or even to take into account the mask manufacturability issues for an additional design cycle.
One of the Crystal work packages is devoted to identification and formalization of recommended design practices to make mask manufacturing a more efficient and less iterative process. Crystal will also provide the tools to deploy and monitor those practices throughout the design chain.
“Designing chips so that photomasks can be manufactured more easily is a complex challenge that cannot be solved without tight collaboration between chip design teams, semiconductor fabs, mask shops and EDA vendors,” said Michel Tissier, European technology integration director at Toppan Photomasks France and head of the Crystal program. “By making these different groups work with Satin IP’s VIP Lane on real manufacturing data, Crystal is expected to help improve design consistency, on-time delivery and the cost of photomask design.”
Michel Tabusse, founder and CEO of Satin IP Technologies, said: “It is Satin IP's core business to help deploy and improve design quality practices throughout semiconductor companies with maximum adoption rate by the design teams.
"Crystal will give us access to real data about the manufacturing challenges at mask shops and about the design practices in the upstream design phases that would solve these challenges. We plan to use these data to create an unmatched library of DFMM quality checks as an add-on to VIP Lane, our design quality closure solution."
Eric Beisser, founder and CEO of XYALIS, added: “Problems that increase the length or number of design cycles, or mistakes that cause additional re-spins of a die, can make the difference between profit and loss for a new product or even result in project cancellation. With photomask manufacturing costs representing almost 10 percent of global costs at the 65nm node, we expect that the DFMM practices that Crystal is documenting for the design community will be of very significant impact.”
The Crystal program was started in January 2008. A design environment prototype, offering a first set of design rules with monitoring capabilities and links to mask data preparation tools, was demonstrated during the Euro Nanoelectronics Forum in Paris (December 2-3, 2008).
An updated prototype will be shown at the Satin IP booth, # 1825, at the Design Automation Conference (San Francisco, July 27-30).
Crystal is a European collaborative R&D program sponsored by the Cluster for Application and Technology Research in Europe on NanoElectronics (CATRENE). Other participants include Atmel and CEA-LETI.
While the old design rule checkers (DRC) developed into sophisticated and pro-active design for manufacturing (DFM) tool suites, the mask rules checks are still implemented at the final phase when the GDSII data is released.
Resolution enhancement techniques (RET) and optical proximity correction (OPC) further restrict the ability to revise the design or even to take into account the mask manufacturability issues for an additional design cycle.
One of the Crystal work packages is devoted to identification and formalization of recommended design practices to make mask manufacturing a more efficient and less iterative process. Crystal will also provide the tools to deploy and monitor those practices throughout the design chain.
“Designing chips so that photomasks can be manufactured more easily is a complex challenge that cannot be solved without tight collaboration between chip design teams, semiconductor fabs, mask shops and EDA vendors,” said Michel Tissier, European technology integration director at Toppan Photomasks France and head of the Crystal program. “By making these different groups work with Satin IP’s VIP Lane on real manufacturing data, Crystal is expected to help improve design consistency, on-time delivery and the cost of photomask design.”
Michel Tabusse, founder and CEO of Satin IP Technologies, said: “It is Satin IP's core business to help deploy and improve design quality practices throughout semiconductor companies with maximum adoption rate by the design teams.
"Crystal will give us access to real data about the manufacturing challenges at mask shops and about the design practices in the upstream design phases that would solve these challenges. We plan to use these data to create an unmatched library of DFMM quality checks as an add-on to VIP Lane, our design quality closure solution."
Eric Beisser, founder and CEO of XYALIS, added: “Problems that increase the length or number of design cycles, or mistakes that cause additional re-spins of a die, can make the difference between profit and loss for a new product or even result in project cancellation. With photomask manufacturing costs representing almost 10 percent of global costs at the 65nm node, we expect that the DFMM practices that Crystal is documenting for the design community will be of very significant impact.”
The Crystal program was started in January 2008. A design environment prototype, offering a first set of design rules with monitoring capabilities and links to mask data preparation tools, was demonstrated during the Euro Nanoelectronics Forum in Paris (December 2-3, 2008).
An updated prototype will be shown at the Satin IP booth, # 1825, at the Design Automation Conference (San Francisco, July 27-30).
Tuesday, 7 July 2009
Replisaurus, Leti drive metallization technology into final stages
KISTA, SWEDEN: Replisaurus Technologies, Inc. announced a common laboratory agreement with CEA-Leti, which maintains one of the world's leading research centers for applied electronics in Grenoble, France.
The agreement marks a major step towards commercialization of Replisaurus’ innovative ElectroChemical Pattern Replication (ECPR) metallization process, and allows the company to move full speed ahead as it prepares to meet the high-volume, short cycle demands of the device interconnect market.
Under the multi-year agreement, Replisaurus and Leti personnel will collaborate and take advantage of the lab's extensive manufacturing facilities, experience in both semiconductor and MEMS technology, and expertise with 200mm and 300mm wafer technologies.
The team will initially focus on optimizing the development of reusable master electrodes, a key component of the ECPR process which employs a template to fabricate metal patterns in a single replication step. They will also investigate the opportunities for ECPR in new applications, notably in key growth sectors such as integrated passives, copper pillars and 3D integration.
The team will optimize electrode design and fabrication flow for each application area, ensuring the best yield, endurance and cycle time.
In order to create a platform to build its mastering business, Replisaurus has started a new company called Replisaurus Mastering, and the program is already up and running at Leti's facility in Grenoble.
"The mastering process is a central part of our business model and a unique component of our technology, so Leti's practical, business-oriented approach to IP rights was a major factor in our decision to partner with them,” said James Quinn, CEO of Replisaurus. “We are moving forward according to plans to roll out our technology, and through this partnership Leti will support us in transferring it to a foundry partner.”
The ECPR process reduces metallization complexity and accelerates production by eliminating many steps from the traditional process. ECPR also provides improved patterning and significant cost and time savings, with a fab-friendly, environmentally clean process that doesn't use solvents or strippers.
Along with its significant environmental benefits, ECPR reduces metallization complexity, boosts production speed, and represents a genuine step forward for the chip industry.
The agreement marks a major step towards commercialization of Replisaurus’ innovative ElectroChemical Pattern Replication (ECPR) metallization process, and allows the company to move full speed ahead as it prepares to meet the high-volume, short cycle demands of the device interconnect market.
Under the multi-year agreement, Replisaurus and Leti personnel will collaborate and take advantage of the lab's extensive manufacturing facilities, experience in both semiconductor and MEMS technology, and expertise with 200mm and 300mm wafer technologies.
The team will initially focus on optimizing the development of reusable master electrodes, a key component of the ECPR process which employs a template to fabricate metal patterns in a single replication step. They will also investigate the opportunities for ECPR in new applications, notably in key growth sectors such as integrated passives, copper pillars and 3D integration.
The team will optimize electrode design and fabrication flow for each application area, ensuring the best yield, endurance and cycle time.
In order to create a platform to build its mastering business, Replisaurus has started a new company called Replisaurus Mastering, and the program is already up and running at Leti's facility in Grenoble.
"The mastering process is a central part of our business model and a unique component of our technology, so Leti's practical, business-oriented approach to IP rights was a major factor in our decision to partner with them,” said James Quinn, CEO of Replisaurus. “We are moving forward according to plans to roll out our technology, and through this partnership Leti will support us in transferring it to a foundry partner.”
The ECPR process reduces metallization complexity and accelerates production by eliminating many steps from the traditional process. ECPR also provides improved patterning and significant cost and time savings, with a fab-friendly, environmentally clean process that doesn't use solvents or strippers.
Along with its significant environmental benefits, ECPR reduces metallization complexity, boosts production speed, and represents a genuine step forward for the chip industry.
Monday, 6 July 2009
TSMC joins CEA-Leti program on multiple e-beam lithography
HSINCHU, TAIWAN & GRENOBLE, FRANCE: TSMC and CEA-Leti, the leading French semiconductor research institute, signed an agreement where TSMC will join the new industrial program IMAGINE, led by CEA-Leti, on maskless lithography for IC manufacturing.
Intended to operate for three years, this program allows companies to assess a maskless lithography infrastructure for IC manufacturing and use MAPPER Technology as a solution towards high throughput. It covers a global approach, including tool assessment, patterning and process integration, data handling, prototyping and cost analysis.
“TSMC is always pushing for cost-effective lithography and the development of maskless lithography is one of the potential solutions. We have already announced the joint steps with Mapper to explore multiple e-beam lithography for IC manufacturing at 22 nanometer node and beyond,” said TSMC’s VP of R&D, Jack Sun.
“By joining the IMAGINE program at CEA-Leti, we intend to federate the semiconductor industry around this technology and accelerate its development and introduction for IC manufacturing.”
“Lithography is a major challenge for the industry. A maskless approach can offer flexibility and gain in cost of ownership. Together with MAPPER, we see a route towards industrial throughput,” said Leti’s CEO, Laurent Malier.
“Having TSMC on board the IMAGINE program is pivotal and will strengthen the assessment towards manufacturing. It shows the commitment in the technology from the industry and will take maskless lithography to the next step in the development that is required to make it a viable solution for 22nm manufacturing.”
Intended to operate for three years, this program allows companies to assess a maskless lithography infrastructure for IC manufacturing and use MAPPER Technology as a solution towards high throughput. It covers a global approach, including tool assessment, patterning and process integration, data handling, prototyping and cost analysis.
“TSMC is always pushing for cost-effective lithography and the development of maskless lithography is one of the potential solutions. We have already announced the joint steps with Mapper to explore multiple e-beam lithography for IC manufacturing at 22 nanometer node and beyond,” said TSMC’s VP of R&D, Jack Sun.
“By joining the IMAGINE program at CEA-Leti, we intend to federate the semiconductor industry around this technology and accelerate its development and introduction for IC manufacturing.”
“Lithography is a major challenge for the industry. A maskless approach can offer flexibility and gain in cost of ownership. Together with MAPPER, we see a route towards industrial throughput,” said Leti’s CEO, Laurent Malier.
“Having TSMC on board the IMAGINE program is pivotal and will strengthen the assessment towards manufacturing. It shows the commitment in the technology from the industry and will take maskless lithography to the next step in the development that is required to make it a viable solution for 22nm manufacturing.”
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