SAN JOSE, USA: Cadence Design Systems Inc. announced that Fuji Electric Device Technology Co. Ltd. cut development costs by about a third by using the Cadence Virtuoso Accelerated Parallel Simulator.
The company, a leader in power management ICs, credited the simulator with helping design teams boost the quality of their chips, and get them to market faster.
Fuji Electric Device Technology develops high-voltage and high-efficiency AC/DC IC for green IDC power management, communication and automotive markets. To verify a full-chip power system, a simulation technology with high performance and full SPICE accuracy was required.
“The Virtuoso Accelerated Parallel Simulator enabled our design teams to reduce the number of prototyping iterations, leading to a 30 percent reduction in our development costs,” said Takashi Kobayashi, general manager, Semiconductor Device R&D Dept., Electron Device Laboratory, Semiconductors Group, Fuji Electric Device Technology Co. Ltd.
“Using the Accelerated Parallel Simulator, we have reduced simulation time up to 75 percent for our full-chip designs without sacrificing any accuracy. As a result we are able to deliver high-quality devices and meet the market window.”
“We’re glad to see Fuji Electric Device Technology place its logo alongside the many other leading technology companies who have discovered the capabilities and benefits of the Virtuoso Accelerated Parallel Simulator for small to large pre layout and post layout designs,” said Zhihong Lui, corporate vice president at Cadence.
“The company’s experience of quality improvements and faster time to market is wholly consistent with what we’ve been hearing from other companies as well.”
Part of the Virtuoso Multi-mode Simulation, the Virtuoso Accelerated Parallel Simulator provides the next generation SPICE accurate simulation, with scalable performance and capacity, for a broad class of complex analog, RF and mixed-signal blocks and sub-systems with ten thousands of devices.
It is tightly integrated with the Virtuoso custom design platform and provides all the transistor-level analysis capabilities as in Virtuoso Spectre Simulator. The proprietary full matrix-solving algorithm delivers unparalleled scalable multi-threading capability using modern multi-core machines.
Showing posts with label Virtuoso Accelerated Parallel Simulator. Show all posts
Showing posts with label Virtuoso Accelerated Parallel Simulator. Show all posts
Monday, 28 September 2009
Tuesday, 16 June 2009
Cadence Virtuoso APS boosts Kaben's performance by 7X
SAN JOSE, USA: Cadence Design Systems Inc. announced that Kaben Wireless Silicon has achieved dramatic performance boosts while running top-level simulations using the Cadence Virtuoso Accelerated Parallel Simulator (APS).
Kaben, a leading provider of RFIC semiconductor IP for next-generation wireless communication, also credits the Virtuoso Accelerated Parallel Simulator with enabling engineers to find and resolve design issues that they believe they would have missed without the performance and capacity delivered by APS.
The simulator was introduced in December, and to date Kaben has achieved impressive results, including one case where Kaben achieved a 7.6 times performance boost with four threads over the baseline SPICE simulator on a pre-layout PLL design with fewer than 5,000 devices.
In the case of a post-layout PLL design with 328,000 devices dominated by parasitics, the Virtuoso Accelerated Parallel Simulator ran the complete simulation without reducing the design net list in four days with full SPICE accuracy compared to a previous solution where they were not even able to run the simulation.
“Because of its quick run time and high-capacity, the Virtuoso Accelerated Parallel Simulator helped our team find design issues early on in the verification phase, then quickly fix them and run another iteration of verification,” said Tom Riley, chief technology officer of Kaben Wireless Silicon.
“The ability to perform high-capacity post-layout simulations quickly, for fully functional and integrated transceiver IP, with full SPICE accuracy and scalable performance across a multi-compute platform is a real enabler for our efforts to deliver turnkey wireless applications to our customers.”
The Virtuoso Accelerated Parallel Simulator also enables Kaben to run simulations at new levels of abstraction. Kaben engineers can get more coverage across various corners and conditions in less time than required by previous solutions. The simulator can be accessed through a flexible token-based licensing model.
The Virtuoso Accelerated Parallel Simulator delivers the full accuracy of the industry reference Cadence Virtuoso Spectre Circuit Simulator. Developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, it consists of a combination of proven Cadence simulation technologies and a breakthrough parallel circuit solver, along with a newly architected engine that efficiently harnesses the power of multiprocessing computing platforms.
The result is a circuit simulator with an accuracy and use model identical to the Virtuoso Spectre Circuit Simulator, delivering significantly improved single-thread performance and scalable multi-thread performance.
“Kaben Wireless Silicon’s designs are, by necessity, very complex components, and therefore comprehensive simulations are a necessity to help ensure they meet customer specifications,” said Zhihong Liu, corporate vice president of Cadence. “Kaben is seeing firsthand how the Virtuoso Accelerated Parallel Simulator delivers comprehensive simulation, and helps ensure market opportunities are realized.”
Kaben, a leading provider of RFIC semiconductor IP for next-generation wireless communication, also credits the Virtuoso Accelerated Parallel Simulator with enabling engineers to find and resolve design issues that they believe they would have missed without the performance and capacity delivered by APS.
The simulator was introduced in December, and to date Kaben has achieved impressive results, including one case where Kaben achieved a 7.6 times performance boost with four threads over the baseline SPICE simulator on a pre-layout PLL design with fewer than 5,000 devices.
In the case of a post-layout PLL design with 328,000 devices dominated by parasitics, the Virtuoso Accelerated Parallel Simulator ran the complete simulation without reducing the design net list in four days with full SPICE accuracy compared to a previous solution where they were not even able to run the simulation.
“Because of its quick run time and high-capacity, the Virtuoso Accelerated Parallel Simulator helped our team find design issues early on in the verification phase, then quickly fix them and run another iteration of verification,” said Tom Riley, chief technology officer of Kaben Wireless Silicon.
“The ability to perform high-capacity post-layout simulations quickly, for fully functional and integrated transceiver IP, with full SPICE accuracy and scalable performance across a multi-compute platform is a real enabler for our efforts to deliver turnkey wireless applications to our customers.”
The Virtuoso Accelerated Parallel Simulator also enables Kaben to run simulations at new levels of abstraction. Kaben engineers can get more coverage across various corners and conditions in less time than required by previous solutions. The simulator can be accessed through a flexible token-based licensing model.
The Virtuoso Accelerated Parallel Simulator delivers the full accuracy of the industry reference Cadence Virtuoso Spectre Circuit Simulator. Developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, it consists of a combination of proven Cadence simulation technologies and a breakthrough parallel circuit solver, along with a newly architected engine that efficiently harnesses the power of multiprocessing computing platforms.
The result is a circuit simulator with an accuracy and use model identical to the Virtuoso Spectre Circuit Simulator, delivering significantly improved single-thread performance and scalable multi-thread performance.
“Kaben Wireless Silicon’s designs are, by necessity, very complex components, and therefore comprehensive simulations are a necessity to help ensure they meet customer specifications,” said Zhihong Liu, corporate vice president of Cadence. “Kaben is seeing firsthand how the Virtuoso Accelerated Parallel Simulator delivers comprehensive simulation, and helps ensure market opportunities are realized.”
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