MOUNTAIN VIEW, USA: Synopsys Inc. today announced its complete DesignWare IP solution for PCI Express (PCIe) 3.0 consisting of digital controllers, PHY and verification IP. PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG) at a preliminary revision 0.5.
Synopsys' high-quality DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise computing applications.
Built on the trusted DesignWare IP for PCI Express 2.0 and 1.x architecture, which has been silicon-proven in more than 250 SoC designs, the DesignWare IP for PCI Express 3.0 allows designers to quickly incorporate the new PCI Express 3.0 features into their products with less risk and improved time to market.
For over 15 years, Synopsys has consistently been a technology leader in PCI and PCI Express IP. Synopsys' work with leading technology companies in the PCI Express ecosystem has led to a number of key contributions to the industry, including the release of the industry's first complete PCI Express 2.0 IP solution.
In addition, the DesignWare IP for PCI Express with PCI-SIG Single Root I/O Virtualization (SR-IOV) Technology was used as the gold standard in the SR-IOV lab at the 2008 Intel Developers Forum to showcase SR-IOV technology.
Synopsys is continuing this technology leadership and leveraging its expertise to provide early availability of the PCI Express 3.0 IP, enabling designers to develop products in conjunction with the ongoing development of the PCI Express 3.0 specification and deliver compliant products soon after the initial public release of the specification.
"Synopsys has been an active member of the PCI-SIG since 2003, participating in the working groups and contributing to the evolution of the PCI Express specification," said Al Yanes, PCI-SIG chairman and president. "As a provider of PCI Express IP, Synopsys supports the latest version of the PCI Express 3.0 specification to help facilitate the early adoption of PCI Express 3.0 into the enterprise computing market segment."
Synopsys invests significantly to ensure the DesignWare IP for PCI Express is interoperable with other PCI Express-based products in the market. As a result, Synopsys' DesignWare IP for PCI Express is used in Agilent's Protocol Test Cards (PTC), a required Gold Test at the PCI-SIG compliance workshops.
The DesignWare IP is also the first IP to pass Agilent's Jammer in-line error injection testing, which injects disruptive test scenarios to test the reliability and robustness of the PCI Express design.
Using Synopsys' high-quality development methodology helps ensure the new DesignWare IP solution for PCI Express 3.0 provides the same level of interoperability and strict adherence to the PCI Express standard as the existing DesignWare IP for PCI Express solutions.
"Neterion is at the forefront of developing high-performance products for the enterprise computing market and PCI Express is a key technology for our product roadmap," said Dennis Shwed, vice president of hardware development at Neterion.
"We have been very successful in incorporating the Synopsys DesignWare IP for PCI Express in our current products and are excited to see Synopsys aggressively embrace PCI Express 3.0. This is exactly what we have come to expect from an industry leader like Synopsys."
Synopsys' suite of digital controllers for PCI Express 3.0 is based on the DesignWare IP for PCI Express 2.0/1.1 architecture, allowing designers to benefit from small area and low latency to reduce costs and improve overall system throughput. The DesignWare digital controllers for PCI Express 3.0 implement the same interfaces as PCI Express 2.0, allowing customers to quickly upgrade to PCI Express 3.0.
For the physical layer, Synopsys is developing a PHY architecture specifically optimized for PCI Express 3.0 with high-performance margins to allow the PHY to achieve the final PCI Express 3.0 specifications in areas such as jitter, margin, and receive sensitivity.
In addition, the advanced built-in diagnostic capabilities and ATE test vectors enable at-speed product testing of the DesignWare PHY IP for PCI Express 3.0 and on-chip visibility into the actual link performance.
Complementing the digital controllers and PHY is the DesignWare Verification IP for PCI Express 3.0, which supports directed testing and constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog and allows designers to create complex protocol test scenarios for verifying their SoCs.
"The enterprise computing market is driving the need for the high-performance PCI Express 3.0 interface in the products our customers expect to be shipping in 2010," said John Koeter, vice president of marketing for the Solutions Group at Synopsys.
"By providing designers with early access to PCI Express 3.0 IP that is based on a proven and trusted architecture, Synopsys lowers the risk of incorporating the PCI Express 3.0 interface into advanced SoCs."
The DesignWare digital controllers and Verification IP for PCI Express 3.0 are available now for selected early adopters. The DesignWare PHYs for PCI Express 3.0 are currently in development for leading foundry processes.
Showing posts with label SoC designs. Show all posts
Showing posts with label SoC designs. Show all posts
Wednesday, 15 July 2009
Wednesday, 1 July 2009
Cadence, Toshiba ally on integrated design environment for COT and SoC design
SAN JOSE, USA: Cadence Design Systems announced an extensive collaboration with Toshiba to address the challenges of existing and next-generation SoC designs.
Toshiba is a leading provider of process and design solution for cutting-edge SoC products. Based on the Cadence Encounter Digital Implementation System and the Cadence Virtuoso Custom Design Solution, the collaboration provides a full digital and mixed-signal design environment to Toshiba and its COT customers for the most advanced semiconductor products where integration of digital and mixed-signal designs is a key to success.
“In highly competitive markets such as wireless and consumer devices designers are expressing a growing requirement for integration of digital and mixed-signal content on ever-smaller semiconductor devices,” said Tatsuo Noguchi, Technology Executive for SoC of Toshiba Corp. Semiconductor Co.
“Because the Cadence Encounter and Virtuoso design environments provide the industry-leading analog and digital design flows necessary to meet these challenges, we are delighted to work closely with Cadence and help our COT customers realize their highly integrated custom IC design. We expect the collaboration to continue to provide benefits to the design community going forward.”
The ongoing collaboration focuses primarily on physical implementation, verification, and custom analog integration for COT and SoC designs. The physical implementation flow includes Cadence Encounter RTL Compiler, Cadence Conformal verification suite, Cadence QRC Extraction and the Encounter Digital Implementation System.
The Toshiba flow utilizes Cadence Encounter Timing System for timing verification, Cadence Physical Verification System for physical verification, Cadence Virtuoso IC 6.1 for custom analog design and Cadence process design kits (PDKs) for quicker, more accurate design.
“Cadence has worked extensively over the years with Toshiba Semiconductor to provide the design environment necessary to meet all the latest challenges to COT and SoC designs,” said Chi-Ping Hsu, senior vice president of the Implementation Products Group at Cadence. “We’re confident that this association will continue to deliver the design flows necessary to create high-quality semiconductor products.”
Toshiba is a leading provider of process and design solution for cutting-edge SoC products. Based on the Cadence Encounter Digital Implementation System and the Cadence Virtuoso Custom Design Solution, the collaboration provides a full digital and mixed-signal design environment to Toshiba and its COT customers for the most advanced semiconductor products where integration of digital and mixed-signal designs is a key to success.
“In highly competitive markets such as wireless and consumer devices designers are expressing a growing requirement for integration of digital and mixed-signal content on ever-smaller semiconductor devices,” said Tatsuo Noguchi, Technology Executive for SoC of Toshiba Corp. Semiconductor Co.
“Because the Cadence Encounter and Virtuoso design environments provide the industry-leading analog and digital design flows necessary to meet these challenges, we are delighted to work closely with Cadence and help our COT customers realize their highly integrated custom IC design. We expect the collaboration to continue to provide benefits to the design community going forward.”
The ongoing collaboration focuses primarily on physical implementation, verification, and custom analog integration for COT and SoC designs. The physical implementation flow includes Cadence Encounter RTL Compiler, Cadence Conformal verification suite, Cadence QRC Extraction and the Encounter Digital Implementation System.
The Toshiba flow utilizes Cadence Encounter Timing System for timing verification, Cadence Physical Verification System for physical verification, Cadence Virtuoso IC 6.1 for custom analog design and Cadence process design kits (PDKs) for quicker, more accurate design.
“Cadence has worked extensively over the years with Toshiba Semiconductor to provide the design environment necessary to meet all the latest challenges to COT and SoC designs,” said Chi-Ping Hsu, senior vice president of the Implementation Products Group at Cadence. “We’re confident that this association will continue to deliver the design flows necessary to create high-quality semiconductor products.”
Monday, 22 June 2009
Tensilica's high-performance ConnX DSP family for LTE and 4G SoC designs
SANTA CLARA, USA: Tensilica Inc. has introduced a new family of high-performance DSPs (digital signal processors) IP (intellectual property) cores -- the ConnX DSP family -- that includes standard cores, click-box configurable options or a starting point for customized Xtensa LX DPUs (dataplane processor units) for SoC designs.
The newest member of the family, the ConnX Baseband Engine provides industry leading computational throughput (sixteen 18-bit MACs per cycle) due to its application-specific instruction set optimized for compute-intensive LTE and 4G wireless base stations. Tensilica plans other ConnX family members for the low-power requirements of the handset market.
"With its configurable instruction set, Tensilica has morphed its basic Xtensa RISC architecture to become a compelling DSP engine," stated Will Strauss, president of Forward Concepts.
"The company's first giant leap into the DSP world was through the design of their HiFi 2 Audio Engine into cellular phones, Blu-ray Disc players, and other home entertainment products, where they've had considerable success. Now, with the ConnX DSP Baseband Engine, Tensilica is taking aim at the fastest growing part of the market - next generation wireless. They already have major customers - including Fujitsu, Panasonic and NEC -- doing their own designs in this market. I expect they will do quite well with this high-performance DSP engine."
"Our customers are increasingly customizing Xtensa DPUs for both small, power efficient DSP functions and large, complex DSP functions," stated Jack Guedj, Tensilica's president and CEO. "The majority of our over 350 million DPU cores shipped have performed complex DSP functions, such as audio, video, security, and image signal processing. Now, with this family of pre-designed communications DSP cores, our customers will be able to achieve faster time-to-market on their new next-generation of communications SOCs."
Tensilica realizes that there are two very different types of requirements for DSPs in wireless systems. The ConnX Baseband Engine fills the more traditional software-centric DSP requirements for base stations, and for multi-mode, multi-standard terminal devices. Tensilica's Xtensa technology can also be optimized to build more narrowly tailored, optimized functional blocks that fit into a hardware-centric design style typically found in wireless handset implementations, and Tensilica plans several products in this area.
The ConnX family of communications DSP engines includes other functions that are in high demand for next-generation compute-intensive tasks. The ConnX Baseband Engine joins the proven quad-MAC Vectra LX DSP option, which is now re-branded as the ConnX Vectra Engine. The ConnX Vectra Engine has been used in many customer designs and is an integral part of the re-branded ConnX 545CK standard DSP.
The ConnX 545CK was previously known as the Diamond 545CK, which received a BDTIsimMark2000 score of 3820. The BDTIsimMark is a summary measure of overall DSP processing speed based on BDTI's DSP Kernel Benchmarks, and the 545CK received the highest BDTIsimMark2000 score of all licensable cores evaluated by BDTI.
The ConnX family of DSP engines includes other functions that are in high demand for next-generation compute-intensive tasks. Tensilica expects that it can quickly leverage its customizable processor technology to develop key functions that will significantly expand its business in several market areas.
The newest member of the family, the ConnX Baseband Engine provides industry leading computational throughput (sixteen 18-bit MACs per cycle) due to its application-specific instruction set optimized for compute-intensive LTE and 4G wireless base stations. Tensilica plans other ConnX family members for the low-power requirements of the handset market.
"With its configurable instruction set, Tensilica has morphed its basic Xtensa RISC architecture to become a compelling DSP engine," stated Will Strauss, president of Forward Concepts.
"The company's first giant leap into the DSP world was through the design of their HiFi 2 Audio Engine into cellular phones, Blu-ray Disc players, and other home entertainment products, where they've had considerable success. Now, with the ConnX DSP Baseband Engine, Tensilica is taking aim at the fastest growing part of the market - next generation wireless. They already have major customers - including Fujitsu, Panasonic and NEC -- doing their own designs in this market. I expect they will do quite well with this high-performance DSP engine."
"Our customers are increasingly customizing Xtensa DPUs for both small, power efficient DSP functions and large, complex DSP functions," stated Jack Guedj, Tensilica's president and CEO. "The majority of our over 350 million DPU cores shipped have performed complex DSP functions, such as audio, video, security, and image signal processing. Now, with this family of pre-designed communications DSP cores, our customers will be able to achieve faster time-to-market on their new next-generation of communications SOCs."
Tensilica realizes that there are two very different types of requirements for DSPs in wireless systems. The ConnX Baseband Engine fills the more traditional software-centric DSP requirements for base stations, and for multi-mode, multi-standard terminal devices. Tensilica's Xtensa technology can also be optimized to build more narrowly tailored, optimized functional blocks that fit into a hardware-centric design style typically found in wireless handset implementations, and Tensilica plans several products in this area.
The ConnX family of communications DSP engines includes other functions that are in high demand for next-generation compute-intensive tasks. The ConnX Baseband Engine joins the proven quad-MAC Vectra LX DSP option, which is now re-branded as the ConnX Vectra Engine. The ConnX Vectra Engine has been used in many customer designs and is an integral part of the re-branded ConnX 545CK standard DSP.
The ConnX 545CK was previously known as the Diamond 545CK, which received a BDTIsimMark2000 score of 3820. The BDTIsimMark is a summary measure of overall DSP processing speed based on BDTI's DSP Kernel Benchmarks, and the 545CK received the highest BDTIsimMark2000 score of all licensable cores evaluated by BDTI.
The ConnX family of DSP engines includes other functions that are in high demand for next-generation compute-intensive tasks. Tensilica expects that it can quickly leverage its customizable processor technology to develop key functions that will significantly expand its business in several market areas.
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