SAN JOSE, USA: Arasan Chip Systems Inc. a leading provider of Intellectual Property (IP) Cores, announced the release of its MIPI high speed synchronous interface (HSI) controller IP and software stack.
HSI is a full- duplex, low latency protocol, that is optimized for die-level interconnect between an Application Processor and a Baseband chipset. With this release, Arasan continues to offer the most comprehensive portfolio of MIPI IP available in the market today.
The HSI Controller IP and Software Stack are compliant with the HSI v1.0 specification. The IP core is compliant with the HSI Physical Layer Draft v1.1. By integrating this standard interface, application processors and wireless chipset developers are assured of an ecosystem of inter-operable components which can be combined to develop region and application specific mobile platforms.
The HSI physical interface consists of two sets of unidirectional data and control signals combined to form a full-duplex connection. The protocol accommodates up to eight logical channels over this interface with an aggregate bandwidth of 200 Mbps in each direction. Optimized for deployment in mobile platforms, the protocol incorporates features to reduce power through clock gearing and dynamic frequency scaling.
The layered HSI Software Stack is architected to be easily portable to multiple OS's and hardware platforms. The stack can also be used on SoC's that have multiple HSI interfaces. The stack supports multiple priority levels per logical channel and DMA modes for efficient data transfer.
"Mobile platforms need to have the flexibility to support multiple wireless protocols depending on geographic and market conditions," said Somnath Viswanath, Product Marketing Manager at Arasan. "Integrating Arasan's HSI Controller IP and Software Stack provide mobile SoC designers the flexibility to easily connect different HSI based wireless chipsets to their application processor, thereby tailoring their solution for the end market."
Arasan provides a "Total IP Solution" for its MIPI HSI IP. The collateral available for this standard consists of RTL source code for the controller IP, synthesis scripts, test environment, documentation and a Portable Software Stack which are all backed by Arasan's world-class customer support.
Showing posts with label IP cores. Show all posts
Showing posts with label IP cores. Show all posts
Wednesday, 26 August 2009
Monday, 3 August 2009
Altera's CPRI v4.1 IP core for wireless base station and remote radio head design
SAN JOSE, USA: Altera Corp. today announced the availability of its Common Public Radio Interface (CPRI) v4.1 intellectual property (IP) core.
Supporting channel speeds up to 6.144 Gbps, the CPRI v4.1 IP core supports the LTE and WiMAX standards and offers legacy support for WCDMA, CDMA and other air-interface standards in a single system.
It enables developers to easily upgrade from proprietary CPRI implementations to a highly configurable solution supporting today's standards, improving customer productivity and cost of ownership.
This fully configurable, off-the-shelf solution complements Altera's 40-nm portfolio of Arria II GX FPGAs for up to 3.072G CPRI line rates and Stratix IV GX FPGAs and HardCopy IV ASIC solutions for up to 6.144G CPRI line rates.
The IP core targets a wide range of wireless applications including multi-mode air-interface support, single-hop and multi-hop system topologies and advanced MIMO antenna configurations.
It comes complete with test benches that perform start-up sequences for common configuration modes so developers can get up to speed quickly and focus on differentiating their product.
“There is an increasing demand from our customers worldwide to provide off-the-shelf solutions for implementing common functions in wireless basestations,” said Arun Iyengar, senior director of Altera's broadcast and communications business units.
“The Altera CPRI IP core enables customers to minimize design efforts and accelerate time to market for standards-based radio access products while still retaining the ability to customize for the unique requirements of their applications. With increasing demand for bandwidth in the CPRI links, this core combined with our transceiver technology solidly positions OEMs to address future basestation requirements including 10-Gbps CPRI links.”
The Altera CPRI v4.1 IP core includes key features such as:
* Built-in support for CPRI v4.1 and backward compatible mapping methods.
* Line rate support up to 6.144 Gbps requiring a clock rate as low as 153.6 MHz to ease timing closure.
* Up to 24 antenna carriers per IP core.
* Integrated 10/100 Ethernet MAC and HDLC controllers.
“We are pleased that Altera has selected our CPRI v4.1 IP technology to expand their IP portfolio offering,” said Christian Lanzani, senior product manager in Radiocomp ApS. “This technology is the most compact, flexible and in-the-field fully verified CPRI interface solution available for distributed base stations.”
This new CPRI v4.1 core adds to Altera's broad portfolio of wireless basestation technology including IP, reference designs and DSP Builder tool support for creating optimized digital downconverters (DDC), digital upconverters (DUC), crest factor reduction (CFR), digital predistortion (DPD), and other functions.
The CPRI v4.1 core is available either in encrypted IP or as source code for complete user control.
Supporting channel speeds up to 6.144 Gbps, the CPRI v4.1 IP core supports the LTE and WiMAX standards and offers legacy support for WCDMA, CDMA and other air-interface standards in a single system.
It enables developers to easily upgrade from proprietary CPRI implementations to a highly configurable solution supporting today's standards, improving customer productivity and cost of ownership.
This fully configurable, off-the-shelf solution complements Altera's 40-nm portfolio of Arria II GX FPGAs for up to 3.072G CPRI line rates and Stratix IV GX FPGAs and HardCopy IV ASIC solutions for up to 6.144G CPRI line rates.
The IP core targets a wide range of wireless applications including multi-mode air-interface support, single-hop and multi-hop system topologies and advanced MIMO antenna configurations.
It comes complete with test benches that perform start-up sequences for common configuration modes so developers can get up to speed quickly and focus on differentiating their product.
“There is an increasing demand from our customers worldwide to provide off-the-shelf solutions for implementing common functions in wireless basestations,” said Arun Iyengar, senior director of Altera's broadcast and communications business units.
“The Altera CPRI IP core enables customers to minimize design efforts and accelerate time to market for standards-based radio access products while still retaining the ability to customize for the unique requirements of their applications. With increasing demand for bandwidth in the CPRI links, this core combined with our transceiver technology solidly positions OEMs to address future basestation requirements including 10-Gbps CPRI links.”
The Altera CPRI v4.1 IP core includes key features such as:
* Built-in support for CPRI v4.1 and backward compatible mapping methods.
* Line rate support up to 6.144 Gbps requiring a clock rate as low as 153.6 MHz to ease timing closure.
* Up to 24 antenna carriers per IP core.
* Integrated 10/100 Ethernet MAC and HDLC controllers.
“We are pleased that Altera has selected our CPRI v4.1 IP technology to expand their IP portfolio offering,” said Christian Lanzani, senior product manager in Radiocomp ApS. “This technology is the most compact, flexible and in-the-field fully verified CPRI interface solution available for distributed base stations.”
This new CPRI v4.1 core adds to Altera's broad portfolio of wireless basestation technology including IP, reference designs and DSP Builder tool support for creating optimized digital downconverters (DDC), digital upconverters (DUC), crest factor reduction (CFR), digital predistortion (DPD), and other functions.
The CPRI v4.1 core is available either in encrypted IP or as source code for complete user control.
Wednesday, 29 July 2009
Arasan Chip Systems announces e-MMC 4.4 card controller IP core
SAN JOSE, USA: Arasan Chip Systems Inc., a leading provider of Intellectual Property (IP) cores, announced the availability of the Embedded MultiMedia 4.4 Card Controller IP compliant with the recently ratified JEDEC e-MMC 4.4 standard.
Arasan's e-MMC 4.4 Card Controller enables memory card designers to support the higher bandwidth and new security, card partition features offered by e-MMC 4.4.
e-MMC 4.4 has a peak bandwidth of 104MBps. It incorporates multiple modes for data security including a secure partition accessible only with a pre-assigned security key.
The standard also permits Hosts to partition and manage card memory. e-MMC 4.4 cards support multiple boot modes that simplify system design. The boot partition can be configured for enhanced operation to lower BOM costs by eliminating an extra chip for boot code. These features make e-MMC 4.4 the preferred solution for emerging mobile platforms.
"The increasing features and complexity of mobile systems is driving designers to use e-MMC 4.4 to securely access boot code and manage user data," said Somnath Viswanath, Product Marketing Manager at Arasan.
"Designers incorporating Arasan's e-MMC 4.4 Card Controller can leverage its new features and get a head start in their card development so as to be the first in the market with e-MMC 4.4 cards."
Arasan's e-MMC 4.4 IP core is backward compatible with the prior 4.3 standard. The core supports all e-MMC 4.4 security mechanisms such as a replay protected memory block, password based, power-on, temporary or permanent write protection.
Arasan's e-MMC 4.4 IP supports Secure Trim and Erase operation that guarantee data deletion. A dedicated hardware reset pin provides easy initialization of the card.
The e-MMC 4.4 card can be configured with multiple memory partitions, each with a different performance and endurance parameter tuned to support Host access of data or boot code. The e-MMC 4.4 Card Controller IP can be used to design embedded or removable non-volatile storage.
Arasan provides a "Total IP Solution" for its e-MMC 4.4 Card Controller IP which consists of RTL code, synthesis scripts, test environment and detailed documentation all backed by World-class customer support.
Arasan's e-MMC 4.4 Card Controller enables memory card designers to support the higher bandwidth and new security, card partition features offered by e-MMC 4.4.
e-MMC 4.4 has a peak bandwidth of 104MBps. It incorporates multiple modes for data security including a secure partition accessible only with a pre-assigned security key.
The standard also permits Hosts to partition and manage card memory. e-MMC 4.4 cards support multiple boot modes that simplify system design. The boot partition can be configured for enhanced operation to lower BOM costs by eliminating an extra chip for boot code. These features make e-MMC 4.4 the preferred solution for emerging mobile platforms.
"The increasing features and complexity of mobile systems is driving designers to use e-MMC 4.4 to securely access boot code and manage user data," said Somnath Viswanath, Product Marketing Manager at Arasan.
"Designers incorporating Arasan's e-MMC 4.4 Card Controller can leverage its new features and get a head start in their card development so as to be the first in the market with e-MMC 4.4 cards."
Arasan's e-MMC 4.4 IP core is backward compatible with the prior 4.3 standard. The core supports all e-MMC 4.4 security mechanisms such as a replay protected memory block, password based, power-on, temporary or permanent write protection.
Arasan's e-MMC 4.4 IP supports Secure Trim and Erase operation that guarantee data deletion. A dedicated hardware reset pin provides easy initialization of the card.
The e-MMC 4.4 card can be configured with multiple memory partitions, each with a different performance and endurance parameter tuned to support Host access of data or boot code. The e-MMC 4.4 Card Controller IP can be used to design embedded or removable non-volatile storage.
Arasan provides a "Total IP Solution" for its e-MMC 4.4 Card Controller IP which consists of RTL code, synthesis scripts, test environment and detailed documentation all backed by World-class customer support.
Saturday, 9 May 2009
MIPS announces divestiture of Analog Business Group
MOUNTAIN VIEW, USA: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for home entertainment, communications, networking and portable multimedia markets, announced the divestiture of its Analog Business Group.
Synopsys Inc. acquired the business unit in an all-cash transaction for $22 million, effective immediately.
This transaction enables MIPS Technologies to focus exclusively on its core competencies in microprocessor IP, continuing to build on its leadership position in markets like the digital home and networking, while expanding its presence in other key markets. The Analog Business Group was formed through MIPS' acquisition of Chipidea Microelectronica S.A. in August 2007.
"We believe this action will improve shareholder value, increase profitability, boost our competitive position and enable us to focus all of our resources on solving our customers' most immediate design challenges," said John Bourgoin, MIPS Technologies president and CEO. "MIPS has tremendous opportunities in our industry-leading processor IP, development tools and robust ecosystem, and we are laser-focused on growing our business in these areas. Synopsys has a long-term mixed-signal IP business that will be significantly stronger as a result of this deal."
Synopsys Inc. acquired the business unit in an all-cash transaction for $22 million, effective immediately.
This transaction enables MIPS Technologies to focus exclusively on its core competencies in microprocessor IP, continuing to build on its leadership position in markets like the digital home and networking, while expanding its presence in other key markets. The Analog Business Group was formed through MIPS' acquisition of Chipidea Microelectronica S.A. in August 2007.
"We believe this action will improve shareholder value, increase profitability, boost our competitive position and enable us to focus all of our resources on solving our customers' most immediate design challenges," said John Bourgoin, MIPS Technologies president and CEO. "MIPS has tremendous opportunities in our industry-leading processor IP, development tools and robust ecosystem, and we are laser-focused on growing our business in these areas. Synopsys has a long-term mixed-signal IP business that will be significantly stronger as a result of this deal."
Thursday, 7 May 2009
eASIC accelerates DSP market with new IP cores
SANTA CLARA, USA: eASIC Corp., a provider of NEW ASIC devices, announced the immediate availability of two new DSP IP cores, an FFT and FIR Filter Compiler, to accelerate it’s growing momentum into the high performance DSP market.
The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core, available from eZ-IP Alliance partner Steepest Ascent can process data streams as high as 500 MSPS and with its optimized multiplier-less architecture is perfectly suited to Nextreme and Nextreme-2 architectures.
The addition of mainstream DSP blocks to eASIC’s IP portfolio makes it easier for wireless and video/imaging system designers to rapidly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series NEW ASICs.
FFT and FIR filters are the most widely used algorithms in digital communications and video/imaging systems. The new FIR Filter Compiler enables designers to generate optimal implementations of single or multi-rate filters and also takes advantage of multichannel applications.
Most importantly, the optimized multiplier-less architecture greatly reduces resource usage, boosts performance and eliminates the need for large amounts of hard multipliers typically found in FPGAs today. The FFT core provides optimal implementations for OFDM Wireless systems like LTE & WiMAX. Both IP cores support Nextreme and Nextreme-2 NEW ASICs.
“Many wireless infrastructure and video/imaging designers that are using FPGAs are desperately looking for ways to significantly reduce cost and power consumption of their systems,” said Jasbinder Bhoot, Vice President of Marketing at eASIC. “This new IP portfolio will make it much simpler and quicker for customers to migrate their expensive and power hungry FPGA-based DSP designs to Nextreme Series NEW ASICs and reduce both power consumption and cost.”
“The DSP market like many others is currently declining. The availability of lower-cost design platforms is a must to help manufacturer’s lower costs and deliver affordable products into the market,” said Will Strauss, President of Forward Concepts. “The addition of these DSP IP cores as part of eASIC’s Nextreme-2 ASIC library will help designers to deliver low cost products faster.”
The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core, available from eZ-IP Alliance partner Steepest Ascent can process data streams as high as 500 MSPS and with its optimized multiplier-less architecture is perfectly suited to Nextreme and Nextreme-2 architectures.
The addition of mainstream DSP blocks to eASIC’s IP portfolio makes it easier for wireless and video/imaging system designers to rapidly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series NEW ASICs.
FFT and FIR filters are the most widely used algorithms in digital communications and video/imaging systems. The new FIR Filter Compiler enables designers to generate optimal implementations of single or multi-rate filters and also takes advantage of multichannel applications.
Most importantly, the optimized multiplier-less architecture greatly reduces resource usage, boosts performance and eliminates the need for large amounts of hard multipliers typically found in FPGAs today. The FFT core provides optimal implementations for OFDM Wireless systems like LTE & WiMAX. Both IP cores support Nextreme and Nextreme-2 NEW ASICs.
“Many wireless infrastructure and video/imaging designers that are using FPGAs are desperately looking for ways to significantly reduce cost and power consumption of their systems,” said Jasbinder Bhoot, Vice President of Marketing at eASIC. “This new IP portfolio will make it much simpler and quicker for customers to migrate their expensive and power hungry FPGA-based DSP designs to Nextreme Series NEW ASICs and reduce both power consumption and cost.”
“The DSP market like many others is currently declining. The availability of lower-cost design platforms is a must to help manufacturer’s lower costs and deliver affordable products into the market,” said Will Strauss, President of Forward Concepts. “The addition of these DSP IP cores as part of eASIC’s Nextreme-2 ASIC library will help designers to deliver low cost products faster.”
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