MOUNTAIN VIEW, USA: Synopsys Inc. today announced the broad availability of silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of Synopsys' DesignWare IP portfolio.
Synopsys' DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
The IP is available in leading process technologies from 90-nm down to 40-nm, and includes sample software drivers for system development. Synopsys' HDMI IP solution is differentiated in terms of feature set, available process nodes and worldwide technical support.
The DesignWare HDMI IP offering includes a comprehensive set of IP deliverables that helps designers quickly embed this complex interface into next generation multimedia SoCs with less risk. Furthermore, the DesignWare HDMI IP solution provides differentiated features including:
* Superior analog front end to support longer HDMI cables, while maintaining high performance.
* Configurable RTL allow designers to optimize gate count and power consumption by choosing only the features required in their application.
* Built-in (on-die) termination resistors for lower bill-of-materials.
* Numerous optional features as well as a choice of various video and audio interfaces for ease of integration.
"HDMI is one of fastest growing multimedia interfaces and is gaining wide-spread acceptance as the standard for communicating between high-performance digital devices," said Paul O'Donovan, principal analyst at Gartner.
"Our research indicates exponential growth in the number of HDMI ports for mobile/portable markets such as camcorders and cameras. HDMI IP will play a key role in enabling designers to integrate the HDMI interface in their next-generation systems."
"Valens continues to develop next generation products for the high definition home entertainment market, and we chose Synopsys to provide us with a high-quality, compliant HDMI IP solution that would help us quickly implement the latest functionality into our advanced SoCs," said Massad Eyal, vice president of research and development R&D at Valens Semiconductor.
"Synopsys' silicon-proven DesignWare HDMI IP enables us to deliver compelling products to the market faster and with significantly less risk."
"HDMI has emerged as the de-facto multimedia interface standard for high-definition consumer electronics and mobile devices," said John Koeter, vice president of marketing for the Solutions Group.
"With Synopsys' extensive customer base, established sales and support infrastructure, and vast porting capabilities, designers can turn to a trusted HDMI IP solution that can be integrated into their SoC with less risk and improved time-to-market."
The DesignWare HDMI 1.3 Transmit and Receive Controllers and PHY IP are available now in leading 90-nm, 65-nm, 45-nm, and 40-nm process technologies. The DesignWare HDMI 1.4 IP solution is currently in development and anticipated to be available at the end of 2009.
Showing posts with label HDMI. Show all posts
Showing posts with label HDMI. Show all posts
Thursday, 13 August 2009
Friday, 7 August 2009
Mentor's Questa multi-view verification components library supports HDMI
WILSONVILLE, USA: Mentor Graphics Corp. announced that the Questa Multi-view Verification Components (MVC) library now supports HDMI (High-Definition Multimedia Interface), a compact audio/video interface for transmitting uncompressed digital data.
The Questa MVC library helps speed up functional verification of integrated circuits (ICs) incorporating HDMI interface logic, and drastically improves verification coverage for today’s complex multi-media platforms.
Lowering barriers to mixed-abstraction verification
The complexity of today’s SoC verification environments often requires designers to spend valuable time building and verifying multiple, and usually incompatible, verification models of a single block to support system-level, TLM-level and RTL-level verification.
This lack of consistency prevents teams from easily moving up and down in abstraction and maximizing verification effectiveness.
Mentor’s unique Questa Multi-view Verification Components can connect to any level of abstraction from system to gates –- ensuring consistent model behavior and giving the verification team more options to improve performance and increase coverage. The multi-view technology greatly reduces debug time through recognition of protocol stacks.
This allows simulation results, from RTL verification, to be viewed as sequences of initiated transactions and responses, with the RTL signal activity correlated to a higher level transaction view of activity.
Each protocol, such as the HDMI, supported by the Questa MVC library includes a verification plan with full coverage metrics that integrates with the Questa Verification Management system. The verification plan easily incorporates into hierarchical full-chip verification plans.
Questa Verification Management provides visibility into the status of the verification process by providing correlation of coverage metrics to the verification plan.
“The MVC library, which is written in SystemVerilog, supports OVM 2.0 with stimulus generation, reference checking, monitoring and functional coverage for popular protocols such as HDMI,” said Stephen Bailey, director of product marketing for the Design Verification Technology Division of Mentor.
“This enables fast development of tests for all aspects of standard protocols for directed and constrained-random verification environments.”
Questa MVC support for HDMI is available immediately.
Questa functional verification platform
The Questa functional verification platform combines high-performance and high-capacity with the most comprehensive verification capabilities in the industry.
Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB).
Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM 2.0) that delivers unrivaled language and feature support in any design and verification flow.
The Questa MVC library helps speed up functional verification of integrated circuits (ICs) incorporating HDMI interface logic, and drastically improves verification coverage for today’s complex multi-media platforms.
Lowering barriers to mixed-abstraction verification
The complexity of today’s SoC verification environments often requires designers to spend valuable time building and verifying multiple, and usually incompatible, verification models of a single block to support system-level, TLM-level and RTL-level verification.
This lack of consistency prevents teams from easily moving up and down in abstraction and maximizing verification effectiveness.
Mentor’s unique Questa Multi-view Verification Components can connect to any level of abstraction from system to gates –- ensuring consistent model behavior and giving the verification team more options to improve performance and increase coverage. The multi-view technology greatly reduces debug time through recognition of protocol stacks.
This allows simulation results, from RTL verification, to be viewed as sequences of initiated transactions and responses, with the RTL signal activity correlated to a higher level transaction view of activity.
Each protocol, such as the HDMI, supported by the Questa MVC library includes a verification plan with full coverage metrics that integrates with the Questa Verification Management system. The verification plan easily incorporates into hierarchical full-chip verification plans.
Questa Verification Management provides visibility into the status of the verification process by providing correlation of coverage metrics to the verification plan.
“The MVC library, which is written in SystemVerilog, supports OVM 2.0 with stimulus generation, reference checking, monitoring and functional coverage for popular protocols such as HDMI,” said Stephen Bailey, director of product marketing for the Design Verification Technology Division of Mentor.
“This enables fast development of tests for all aspects of standard protocols for directed and constrained-random verification environments.”
Questa MVC support for HDMI is available immediately.
Questa functional verification platform
The Questa functional verification platform combines high-performance and high-capacity with the most comprehensive verification capabilities in the industry.
Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB).
Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM 2.0) that delivers unrivaled language and feature support in any design and verification flow.
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