WILSONVILLE, USA: Mentor Graphics Corp. announced that its Calibre nmDRC and nmLVS offerings now support the interoperable iDRC and iLVS formats introduced by TSMC.
TSMC and Mentor Graphics collaborated on these vendor-neutral formats for describing physical verification and layout vs. schematic (LVS) checks. The iDRC and iLVS syntaxes make it possible for TSMC and its customers to create verification decks that will work with Mentor’s Calibre nmDRC and nmLVS offerings or other verification products that support the specification. Mentor will optimize the underlying implementation of iDRC/iLVS to deliver optimum performance to end users.
The iDRC and iLVS specifications are based on the open source TCL language extended with specialized functions for verification. It has been validated on the Calibre platform for 40nm designs manufactured at TSMC, and will be rolled out as part of the TSMC reference flow for 28nm designs.
“The TSMC iDRC ands iLVS formats benefit both TSMC and its customers by making it possible to define and customize complex verification rules for each of our processes that can in turn drive verification tools from any supporting vendor,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC.
“This enables us and our customers to easily adapt design rules to new requirements or special situations without worrying about tuning and testing for different tool flows. We’ve worked closely with Mentor on the architecture and syntax of iDRC and iLVS and have completed first validation on the Calibre tool suite as our lead physical verification platform.”
“Our collaboration with TSMC on the definition of iDRC and iLVS helps our mutual customers realize the best possible performance from Calibre products,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.
“With this collaboration, TSMC ensures their design guidelines are delivered in a consistent manner to all qualified vendors, and Mentor can use its proprietary technology to continue delivering industry-leading verification platforms with the fastest and most efficient underlying code possible.”
The Calibre implementation of iDRC and iLVS converts iDRC decks into highly tuned native Calibre SVRF calls for optimum runtime performance. It also includes an interactive TCL debugger with breakpoints and variable monitors integrated with a layout debugger, which is part of the Calibre Results Viewing Environment (RVE), and a special in-line SVRF viewer.
The Calibre implementation of iDRC is currently being evaluated at selected TSMC and Mentor customer sites. General availability is expected at the end of 2009.
Showing posts with label Calibre. Show all posts
Showing posts with label Calibre. Show all posts
Sunday, 26 July 2009
Tuesday, 26 May 2009
Fujitsu Microelectronics adopts Mentor's Calibre design-to-silicon platform
WILSONVILLE, USA: Mentor Graphics Corp. announced that Fujitsu Microelectronics Ltd has qualified and adopted the Calibre design-to-silicon platform for physical verification and design-for-manufacturing (DFM) of advanced IC products.
Fujitsu Microelectronics’ Mentor-based flow includes the sign-off standard Calibre verification platform with Calibre nmDRC, LVS, and xRC tools, and Mentor’s comprehensive DFM solution for manufacturing variability, an integrated tool suite for critical area analysis, litho-friendly design, and 3D variability.
The 3D variability solution provides improved planarity by enabling highly optimized fill based on either complex geometry-based rules, or full thickness (CMP) simulation.
“Fujitsu Microelectronics' leading-edge technologies require tight control over thickness variation. Density-based fill is a starting point and an improvement over traditional dummy fill, but at smaller features sizes our analysis shows that we need to consider more than just density,” said Noboru Yokota, General Manager of the Technology Development Division at Fujitsu Microelectronics. “The Mentor solution is unique because it can handle complex equations combining all the factors required to compute an optimum fill that achieves our planarity goals with as few added shapes as possible.”
“Our long-term partnership with Fujitsu Microelectronics has resulted in a complete solution that meets Fujitsu Microelectronics’ verification and DFM requirements for their latest IC designs regardless of which process offering is being targeted,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics.
“Our customers are moving to all-Mentor flows because we offer both the best-in-class technology for each design task, as well as the ease of integration and use that can only be achieved with a single integrated platform and tools built from the ground up to work together seamlessly,” he added.
Mentor’s DFM solution
The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at advanced nodes with better control of manufacturing variability for cell libraries as well as full-chip layouts.
The Calibre DFM solution includes the Calibre LFDproduct, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications.
It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC products, allowing critical device and interconnect characteristics to be extracted based on accurately-modeled, “as-built” contour geometries. The resulting physical data can be plugged into a SPICE simulator to produce an accurate timing simulation of how physical blocks will actually perform.
The Calibre DFM solution includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients.
The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 65nm and below by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.
Fujitsu Microelectronics’ Mentor-based flow includes the sign-off standard Calibre verification platform with Calibre nmDRC, LVS, and xRC tools, and Mentor’s comprehensive DFM solution for manufacturing variability, an integrated tool suite for critical area analysis, litho-friendly design, and 3D variability.
The 3D variability solution provides improved planarity by enabling highly optimized fill based on either complex geometry-based rules, or full thickness (CMP) simulation.
“Fujitsu Microelectronics' leading-edge technologies require tight control over thickness variation. Density-based fill is a starting point and an improvement over traditional dummy fill, but at smaller features sizes our analysis shows that we need to consider more than just density,” said Noboru Yokota, General Manager of the Technology Development Division at Fujitsu Microelectronics. “The Mentor solution is unique because it can handle complex equations combining all the factors required to compute an optimum fill that achieves our planarity goals with as few added shapes as possible.”
“Our long-term partnership with Fujitsu Microelectronics has resulted in a complete solution that meets Fujitsu Microelectronics’ verification and DFM requirements for their latest IC designs regardless of which process offering is being targeted,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics.
“Our customers are moving to all-Mentor flows because we offer both the best-in-class technology for each design task, as well as the ease of integration and use that can only be achieved with a single integrated platform and tools built from the ground up to work together seamlessly,” he added.
Mentor’s DFM solution
The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at advanced nodes with better control of manufacturing variability for cell libraries as well as full-chip layouts.
The Calibre DFM solution includes the Calibre LFDproduct, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications.
It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC products, allowing critical device and interconnect characteristics to be extracted based on accurately-modeled, “as-built” contour geometries. The resulting physical data can be plugged into a SPICE simulator to produce an accurate timing simulation of how physical blocks will actually perform.
The Calibre DFM solution includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients.
The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 65nm and below by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.
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