DUBLIN, IRELAND: Duolog Technologies announced that its award-winning Socrates chip integration platform can now auto-generate a complete OVM verification environment, using version 1.0 of the OVM register package recently released by Mentor Graphics.
Auto-generating a complete OVM verification environment liberates verification teams from the tedious and error-prone task of building and debugging verification environments, allowing them to concentrate on verifying their designs.
“As a member of the Mentor Graphics Questa Vanguard Partnership (QVP) program, Duolog demonstrates the benefits of collaboration to advance verification productivity,” said Dennis Brophy, director of strategic business development, Mentor Graphics. “Duolog’s OVM auto-generation solution accelerates significant user adoption of the OVM 1.0 Register Package.”
The Socrates platform is an Eclipse-based suite of tools for assembling complex SoC, ASIC and FPGA designs. Socrates employs extensive DRC checks to verify design integrity and includes a fully-customizable suite of output generators to auto-create design, verification and software collateral. Auto-generation of design views from a central, verified source ensures that engineering teams remain synchronized at all times, and that costly bugs due to misalignment, miscommunication or misinterpretation are eradicated.
Duolog will be attending DVCon in San Jose, CA from February 22-25. Duolog’s CTO, David Murray, will be demonstrating how the Socrates OVM generators can propel their customers into the highly-productive world of OVM-based verification with minimal effort.
Tuesday, 23 February 2010
Monday, 22 February 2010
Xilinx picks 28nm high–performance, low-power process to accelerate platforms for driving the programmable imperative
INDIA: Xilinx Inc. announced the foundation for a next-generation of Xilinx programmable platforms that will give system designers FPGAs that consume half the power at twice the capacity than previously possible for addressing the Programmable Imperative.
Xilinx is maximizing the value of the 28nm technology node by choosing a high-performance, low-power process technology, a common scalable architecture across product ranges, and tool innovations so customers will have FPGAs that deliver the ASIC-class capabilities they need to meet their cost and power budgets, while improving their productivity through easy design migration and IP reuse.
Today, numerous trends – the exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing – are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.
At the same time, power management and the impact it has on system costs and performance is a paramount concern to today’s electrical system designers and manufacturers. The need to reduce power consumption and manage thermal dissipation, while also keeping ahead on price and performance-driven capabilities, is essential as competitive pressure increases.
“At the 28nm node, static power is a very significant portion of the total power dissipation of a device and in some cases is the dominate factor. To achieve maximal power efficiency, the choice of process technology is paramount because the key to enabling greater useable system performance and capabilities is controlling power consumption,” said Victor Peng, Senior Vice President, Programmable Platforms Development as Xilinx.
“We chose the high-k metal gate high-performance, low-power process at TSMC and Samsung for next-generation FPGAs to significantly minimize static power consumption so we wouldn’t lose the performance and functional advantages we get at 28nm.”
Compared to the standard high-performance process, the high-performance, low-power process delivers FPGAs that are 50 percent lower in static power. The lower static power enables Xilinx to provide customers with the lowest-power FPGAs in their class, and contributes to a 50 percent reduction in total power compared to previous generation devices.
Meanwhile, next-generation development tools reduce dynamic power as much as 20 percent through innovative clock management. Enhancements made to Xilinx’s industry-leading partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33 percent.
To address system performance bottlenecks caused at the interconnect level, Xilinx will provide the industry’s highest performance interfaces to support customers who need high-bandwidth chip-to-chip, board-to-board, and box-to-box connections. This is of critical importance as customers increasingly look to FPGAs to become a major, if not central, component of their systems, and helps define how the next generation of FPGAs will enable customers to build their systems when ASIC and ASSP options are unavailable.
Preserving IP and design investment
Tool enhancements deliver productivity gains in alignment with a unified ASMBL architecture that reduces the need to modify a design to accommodate moving between the range of high-performance and low-cost devices, and ease design migration as Spartan-6 and Virtex-6 FPGA customers transition to the development of their next generation products over time.
Unifying the architecture enables Xilinx to fulfill its vision for ‘socketable IP’ that will allow customers to preserve their IP investments and more easily offer product portfolios that address a broad range of end market requirements. Socketable IP and unification also enables a larger, more responsive ecosystem through reduced IP development cost, all in support of the Xilinx strategy of accelerating innovation and reducing development costs through Targeted Design Platforms.
Xilinx’s collaboration efforts with ARM on the next generation AMBA AXI specification with extensions for FPGA implementation, announced in October 2009, will further drive IP development and re-use by providing software and hardware designers with a proven, broadly adopted standard for interconnecting IP blocks and building embedded systems.
Accelerating platforms to address the programmable imperative
As ASICs and ASSPs become viable for only the highest volume applications, Xilinx’s keen focus on delivering significantly lower-levels of total power consumption is essential for unlocking the full, usable, potential FPGAs can provide systems in support of a variety of applications.
Portable medical equipment, for example, call for low price, small form factor, and low static power to enable battery-powered operation, while reduced thermal dissipation enables higher performance in high-performance computing, electronic warfare and radar systems for the aerospace and defense markets.
The new silicon devices and development tools will form the Base Platform for the next generation of Targeted Design Platforms from Xilinx and 3rd parties, and will include ‘Ultra-High End FPGAs’ that can only be made possible by Xilinx’s process, architectural and tool innovations.
Ultra-high-end FPGAs integrate high serial I/O bandwidth, logic density greater than twice that of what is currently in a high-end FPGA, and high-bandwidth interfaces to next generation memory technology. This enables telecommunications system developers to replace a single large ASIC or an ASSP chip set for applications such as:
High-end Tera-bit switch fabric in telecom systems: Ultra-high-end class FPGAs will enable single-chip implementations of 1Tbps full-duplex switches by integrating the world’s highest serial I/O bandwidth, logic density 2x what’s available in today’s FPGAs, and high-bandwidth interfaces to next generation memory technology replacing a single large ASIC or an ASSP chip set.
400G OTN (optical transport network) line cards: A single ultra-high-end class FPGA can implement the required bandwidth to support multiple 40G or 100G single chip implementations to replace multiple ASSPs on a line card
Built on high-K metal gate, high-performance, low-power 28nm processes at TSMC and Samsung Electronics’ Foundry, initial devices will be available in Q4 of calendar year 2010 with initial tools support available in the ISE Design Suite in June.
Xilinx is maximizing the value of the 28nm technology node by choosing a high-performance, low-power process technology, a common scalable architecture across product ranges, and tool innovations so customers will have FPGAs that deliver the ASIC-class capabilities they need to meet their cost and power budgets, while improving their productivity through easy design migration and IP reuse.
Today, numerous trends – the exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing – are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.
At the same time, power management and the impact it has on system costs and performance is a paramount concern to today’s electrical system designers and manufacturers. The need to reduce power consumption and manage thermal dissipation, while also keeping ahead on price and performance-driven capabilities, is essential as competitive pressure increases.
“At the 28nm node, static power is a very significant portion of the total power dissipation of a device and in some cases is the dominate factor. To achieve maximal power efficiency, the choice of process technology is paramount because the key to enabling greater useable system performance and capabilities is controlling power consumption,” said Victor Peng, Senior Vice President, Programmable Platforms Development as Xilinx.
“We chose the high-k metal gate high-performance, low-power process at TSMC and Samsung for next-generation FPGAs to significantly minimize static power consumption so we wouldn’t lose the performance and functional advantages we get at 28nm.”
Compared to the standard high-performance process, the high-performance, low-power process delivers FPGAs that are 50 percent lower in static power. The lower static power enables Xilinx to provide customers with the lowest-power FPGAs in their class, and contributes to a 50 percent reduction in total power compared to previous generation devices.
Meanwhile, next-generation development tools reduce dynamic power as much as 20 percent through innovative clock management. Enhancements made to Xilinx’s industry-leading partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33 percent.
To address system performance bottlenecks caused at the interconnect level, Xilinx will provide the industry’s highest performance interfaces to support customers who need high-bandwidth chip-to-chip, board-to-board, and box-to-box connections. This is of critical importance as customers increasingly look to FPGAs to become a major, if not central, component of their systems, and helps define how the next generation of FPGAs will enable customers to build their systems when ASIC and ASSP options are unavailable.
Preserving IP and design investment
Tool enhancements deliver productivity gains in alignment with a unified ASMBL architecture that reduces the need to modify a design to accommodate moving between the range of high-performance and low-cost devices, and ease design migration as Spartan-6 and Virtex-6 FPGA customers transition to the development of their next generation products over time.
Unifying the architecture enables Xilinx to fulfill its vision for ‘socketable IP’ that will allow customers to preserve their IP investments and more easily offer product portfolios that address a broad range of end market requirements. Socketable IP and unification also enables a larger, more responsive ecosystem through reduced IP development cost, all in support of the Xilinx strategy of accelerating innovation and reducing development costs through Targeted Design Platforms.
Xilinx’s collaboration efforts with ARM on the next generation AMBA AXI specification with extensions for FPGA implementation, announced in October 2009, will further drive IP development and re-use by providing software and hardware designers with a proven, broadly adopted standard for interconnecting IP blocks and building embedded systems.
Accelerating platforms to address the programmable imperative
As ASICs and ASSPs become viable for only the highest volume applications, Xilinx’s keen focus on delivering significantly lower-levels of total power consumption is essential for unlocking the full, usable, potential FPGAs can provide systems in support of a variety of applications.
Portable medical equipment, for example, call for low price, small form factor, and low static power to enable battery-powered operation, while reduced thermal dissipation enables higher performance in high-performance computing, electronic warfare and radar systems for the aerospace and defense markets.
The new silicon devices and development tools will form the Base Platform for the next generation of Targeted Design Platforms from Xilinx and 3rd parties, and will include ‘Ultra-High End FPGAs’ that can only be made possible by Xilinx’s process, architectural and tool innovations.
Ultra-high-end FPGAs integrate high serial I/O bandwidth, logic density greater than twice that of what is currently in a high-end FPGA, and high-bandwidth interfaces to next generation memory technology. This enables telecommunications system developers to replace a single large ASIC or an ASSP chip set for applications such as:
High-end Tera-bit switch fabric in telecom systems: Ultra-high-end class FPGAs will enable single-chip implementations of 1Tbps full-duplex switches by integrating the world’s highest serial I/O bandwidth, logic density 2x what’s available in today’s FPGAs, and high-bandwidth interfaces to next generation memory technology replacing a single large ASIC or an ASSP chip set.
400G OTN (optical transport network) line cards: A single ultra-high-end class FPGA can implement the required bandwidth to support multiple 40G or 100G single chip implementations to replace multiple ASSPs on a line card
Built on high-K metal gate, high-performance, low-power 28nm processes at TSMC and Samsung Electronics’ Foundry, initial devices will be available in Q4 of calendar year 2010 with initial tools support available in the ISE Design Suite in June.
TI's new green phase-shifted full-bridge controller includes synchronous rectifier output control
DALLAS, USA: Texas Instruments Inc. (TI) has introduced a phase-shifted full-bridge PWM controller with synchronous MOSFET control outputs and light load power management.
The UCC28950 can achieve efficiencies above 90 percent from light load to full load, enabling it to meet 90+ Climate Savers efficiency standards. The device features an adaptive zero voltage switching (ZVS) control scheme with a 10:1 range that can maintain ZVS over wide input voltage variations or output load swings. The wider ZVS operational range saves energy consumption across a broader power output range.
The UCC28950 also has optimized adaptive control for the output synchronous rectifiers including on/off control to optimize efficiency at lighter loads. The UCC28950 is designed for applications like high-power, high-density power supplies; server and telecom power supplies; industrial power systems; solar inverters; electric vehicles; and DC motor drives.
Key features and benefits of the UCC28950
* Synchronous rectifier outputs optimize timing to minimize body diode conduction losses from typical propagation delays, which ensure high efficiency.
* UCC28950 features advanced power management functions that change operational modes under different start-up or load conditions and a burst mode that improves light load or no load efficiency by as much as 70 percent compared to non-green mode solutions. * The UCC28950's programmable ramp compensation allows for current or voltage mode control, adding system flexibility.
* A soft start with enable function allows the UCC28950 to initialize start-up by higher level system control.
* Sync in and sync out function with 90 degrees phase shift for interleaved operation of two parallel power supplies reduces input and output ripple current by 50 to 100 percent. This lower input and output ripple current allows designers to use smaller, lower-cost input and output capacitors.
The UCC28950 is available now in a TSSOP-24 package and is priced at $4.25 in quantities of 1,000.
The UCC28950 can achieve efficiencies above 90 percent from light load to full load, enabling it to meet 90+ Climate Savers efficiency standards. The device features an adaptive zero voltage switching (ZVS) control scheme with a 10:1 range that can maintain ZVS over wide input voltage variations or output load swings. The wider ZVS operational range saves energy consumption across a broader power output range.
The UCC28950 also has optimized adaptive control for the output synchronous rectifiers including on/off control to optimize efficiency at lighter loads. The UCC28950 is designed for applications like high-power, high-density power supplies; server and telecom power supplies; industrial power systems; solar inverters; electric vehicles; and DC motor drives.
Key features and benefits of the UCC28950
* Synchronous rectifier outputs optimize timing to minimize body diode conduction losses from typical propagation delays, which ensure high efficiency.
* UCC28950 features advanced power management functions that change operational modes under different start-up or load conditions and a burst mode that improves light load or no load efficiency by as much as 70 percent compared to non-green mode solutions. * The UCC28950's programmable ramp compensation allows for current or voltage mode control, adding system flexibility.
* A soft start with enable function allows the UCC28950 to initialize start-up by higher level system control.
* Sync in and sync out function with 90 degrees phase shift for interleaved operation of two parallel power supplies reduces input and output ripple current by 50 to 100 percent. This lower input and output ripple current allows designers to use smaller, lower-cost input and output capacitors.
The UCC28950 is available now in a TSSOP-24 package and is priced at $4.25 in quantities of 1,000.
ON Semiconductor intros fixed-frequency current-mode controller for high efficiency, compact adapter solutions
PALM SPRINGS, USA: ON Semiconductor has introduced the NCP1237, NCP1238 and NCP1288 fixed-frequency, current-mode controller ICs.
Targeted at AC-DC adapter applications for laptop/notebook computers, LCD displays, printers and household consumer electronics, the new controllers are available in a choice of frequency options with single or dual-level over-current thresholds. The standard device has a built-in 65 kHz oscillator, with 100 kHz and 133 kHz versions supplied on request.
The proprietary Soft Skip™ mode utilized by these ICs ramp the peak current gradually during skip mode, reducing the risk of audible noise. This allows additional component savings, along with easing the design and manufacture of the transformer. Combining this with a frequency fold-back function, the new controllers deliver high efficiency levels in light load conditions, while minimizing input power during no load conditions.
The Dynamic Self Supply (DSS) function of the NCP1237 and NCP1238 provide an integrated start-up current source that intelligently handles start-up and line transient events. This simplifies the design of the auxiliary supply, reducing the size of the VCC capacitor. To minimize external component count, the controllers integrate brown-out, over-power compensation and ramp compensation, allowing a compact solution to be designed.
The new fixed-frequency, current-mode controller ICs have an operational temperature range of 40ºC to +125ºC, and are offered in a compact SOIC-7 package.
“With utility bills continuing to increase and concerns about the environment growing, it is vital to use electrical power at the greatest possible rates of efficiency,” said Christophe Warin, AC-DC business unit manager at ON Semiconductor. “The NCP1237, NCP1238 and NCP1288 are highly integrated solutions that will allow engineers to develop power system designs that maintain strong reliability, have a low bill-of-materials and do not waste energy when the product is in standby mode.”
Targeted at AC-DC adapter applications for laptop/notebook computers, LCD displays, printers and household consumer electronics, the new controllers are available in a choice of frequency options with single or dual-level over-current thresholds. The standard device has a built-in 65 kHz oscillator, with 100 kHz and 133 kHz versions supplied on request.
The proprietary Soft Skip™ mode utilized by these ICs ramp the peak current gradually during skip mode, reducing the risk of audible noise. This allows additional component savings, along with easing the design and manufacture of the transformer. Combining this with a frequency fold-back function, the new controllers deliver high efficiency levels in light load conditions, while minimizing input power during no load conditions.
The Dynamic Self Supply (DSS) function of the NCP1237 and NCP1238 provide an integrated start-up current source that intelligently handles start-up and line transient events. This simplifies the design of the auxiliary supply, reducing the size of the VCC capacitor. To minimize external component count, the controllers integrate brown-out, over-power compensation and ramp compensation, allowing a compact solution to be designed.
The new fixed-frequency, current-mode controller ICs have an operational temperature range of 40ºC to +125ºC, and are offered in a compact SOIC-7 package.
“With utility bills continuing to increase and concerns about the environment growing, it is vital to use electrical power at the greatest possible rates of efficiency,” said Christophe Warin, AC-DC business unit manager at ON Semiconductor. “The NCP1237, NCP1238 and NCP1288 are highly integrated solutions that will allow engineers to develop power system designs that maintain strong reliability, have a low bill-of-materials and do not waste energy when the product is in standby mode.”
RadiSys intros ruggedized CEQM57XT COM Express module
HILLSBORO, USA: RadiSys Corp., a leading global provider of application-ready software and hardware platforms, has released its ruggedized Procelerant™ CEQM57XT COM Express module for deployment in harsh mil/aero and industrial environments.
The CEQM57XT module combines the Intel Core™ i7 and i5 processors and the Mobile Intel QM57 Express chipset with extended temperature range from -25 to 70 degrees Celsius and ruggedized vibration specifications that are required for many mil/aero and industrial applications such as ruggedized computers/tablets, unmanned vehicles/robots and in-vehicle computers.
By incorporating ruggedness into the product design, RadiSys enables its customers to use the latest technology in harsh environments, saving months of system development time previously dedicated to ensuring that a module can meet their extended temperature or vibration specifications. RadiSys’ proprietary design and test processes set the standard for COM Express ruggedness compared to simple screening processes employed in the industry.
“RadiSys is pleased to introduce our ruggedized CEQM57XT COM Express extended temperature module on the heels of our commercial temperature module release earlier this year, keeping our ruggedized designs on the same technology curve with the industry,” said Lorraine Orcino, RadiSys COM Express Product Line Manager.
“By taking on the responsibility and risk for extended temperature testing, RadiSys is able to give its customers a fast entry to market. Our extended temperature COM Express modules are rapidly being deployed in mil/aero, transportation and industrial applications as an ideal solution for technology insertions and upgrades.”
The CEQM57XT features the Intel Core™ i7 2.53 GHz, 2.0 GHz and 1.06 GHz processors and the Intel Core™ i5 2.4 GHz processor for increased processing performance and a seven-year lifecycle, a key requirement for mil/aero and industrial applications.
RadiSys designs ruggedness into the CEQM57XT by utilizing its proprietary implementation of the Highly Accelerated Life Test (HALT) during the design process to identify and correct product weaknesses prior to production; Highly Accelerated Sample Screen (HASS) is then used during production to continually monitor supplier quality and component robustness. Through rigorous HALT/HASS testing, RadiSys ensures that the product is designed to its extended temperature range limits required by its target markets. If additional humidity ruggedization is required, the CEQM57XT COM Express module is also available with conformal coat Humiseal 1B31 option, providing time and cost savings with a readily available qualified process.
The CEQM57XT module combines the Intel Core™ i7 and i5 processors and the Mobile Intel QM57 Express chipset with extended temperature range from -25 to 70 degrees Celsius and ruggedized vibration specifications that are required for many mil/aero and industrial applications such as ruggedized computers/tablets, unmanned vehicles/robots and in-vehicle computers.
By incorporating ruggedness into the product design, RadiSys enables its customers to use the latest technology in harsh environments, saving months of system development time previously dedicated to ensuring that a module can meet their extended temperature or vibration specifications. RadiSys’ proprietary design and test processes set the standard for COM Express ruggedness compared to simple screening processes employed in the industry.
“RadiSys is pleased to introduce our ruggedized CEQM57XT COM Express extended temperature module on the heels of our commercial temperature module release earlier this year, keeping our ruggedized designs on the same technology curve with the industry,” said Lorraine Orcino, RadiSys COM Express Product Line Manager.
“By taking on the responsibility and risk for extended temperature testing, RadiSys is able to give its customers a fast entry to market. Our extended temperature COM Express modules are rapidly being deployed in mil/aero, transportation and industrial applications as an ideal solution for technology insertions and upgrades.”
The CEQM57XT features the Intel Core™ i7 2.53 GHz, 2.0 GHz and 1.06 GHz processors and the Intel Core™ i5 2.4 GHz processor for increased processing performance and a seven-year lifecycle, a key requirement for mil/aero and industrial applications.
RadiSys designs ruggedness into the CEQM57XT by utilizing its proprietary implementation of the Highly Accelerated Life Test (HALT) during the design process to identify and correct product weaknesses prior to production; Highly Accelerated Sample Screen (HASS) is then used during production to continually monitor supplier quality and component robustness. Through rigorous HALT/HASS testing, RadiSys ensures that the product is designed to its extended temperature range limits required by its target markets. If additional humidity ruggedization is required, the CEQM57XT COM Express module is also available with conformal coat Humiseal 1B31 option, providing time and cost savings with a readily available qualified process.
ARM launches class-leading Cortex-M4 processor for high performance digital signal control
CAMBRIDGE, UK: ARM has launched the innovative Cortex-M4 processor to provide a highly efficient solution for digital signal control (DSC) applications, while maintaining the industry leading capabilities of the ARM Cortex-M family of processors for advanced microcontroller (MCU) applications.
The outstanding combination of high-efficiency signal processing functionality with the unmatched low-power, low cost and ease-of-use benefits of the Cortex-M family processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets.
The Cortex-M4 processor features a single-cycle multiply-accumulate (MAC)unit, optimized single instruction multiple data (SIMD) instructions, saturating arithmetic instructions and an optional single precision Floating-Point Unit (FPU). These digital signal control features build upon the innovative technology that characterizes the ARM Cortex-M family of processors.
These features include a 32-bit core capable of 1.25DMIPS/MHz for high performance, Thumb-2 instructions for optimum code density and a Nested Vector Interrupt Controller for outstanding interrupt handling. In addition, the processor features an optional Memory Protection Unit (MPU), low cost debug/trace and integrated sleep states for increased flexibility. Embedded developers will be able to rapidly design and deliver compelling end-products with maximum functionality and the absolute minimum power and area footprint.
“The signal processing requirements of the embedded market are moving from dedicated processors toward hybrid microcontrollers. These products are capable of delivering outstanding digital signal control while providing the flexibility to efficiently perform other processing operations,” said Will Strauss, president of Forward Concepts, the premier market research firm tracking markets based on digital signal processing (DSP) technology.
“The ARM partnership will capitalize on this shift with the introduction of the Cortex-M4 processor which has all of the capabilities for optimum digital signal control operations combined with the proven low power performance of the Cortex-M family processors.”
The Cortex-M4 processor is supported by the ARM physical IP portfolio offering the widest foundry and technology support for physical implementations. This includes the Cortex-M Low Power Optimization Package for the TSMC CE018FG (180nm ULL) process for Partners targeting ultra low-power implementations.
For Partners targeting high-performance MCU class devices, ARM also provides physical IP solutions on leading foundry processes. For a target frequency of 150MHz for next generation MCU devices, ARM physical IP for the 65nm GLOBALFOUNDRIES 65LPe process enables a standard implementation of the Cortex-M4 processor within just 65K gates and a dynamic power consumption of less than 40µW/MHz. The FPU, if included, adds only 25K gates and enables an extremely powerful implementation within an industry leading area footprint.
Sophisticated development tool support for the Cortex-M4 processor is provided by the Keil MDK-ARM (Microcontroller Development Kit) which includes the industry-standard ARM compiler extended for SIMD and FPU. MDK-ARM also contains µVision4 with complete Cortex-M4 processor instruction simulation as well as target debugging with advanced trace capabilities.
In addition, the processor is supported with development tools, debuggers and RTOS from members of the ARM Connected Community, the industry’s largest ecosystem of companies aligned to provide a complete solution, from design to manufacture, for products based on the ARM architecture.
Cortex Microcontroller Software Interface Standard (CMSIS)
The Cortex-M4 processor is fully supported by the Cortex Microcontroller Software Interface Standard (CMSIS) the vendor-independent hardware abstraction layer for the Cortex-M processor series that enables consistent and simple software interfaces to the processor for peripherals and real-time operating systems.
ARM is currently expanding the CMSIS to include C Compiler support for Cortex-M4 processor extended instructions and is developing an optimized library designed to make signal processing programs easier to develop for MCU users. This library will include digital filter algorithms and general functions such as maths, trigonometric, and control functions. The digital filter algorithms are also intended for use with filter design utilities and design toolkits such as MATLAB and LabVIEW.
In addition, ARM has developed a series of Cortex-M4 hardware and software training courses to ensure licensees can efficiently integrate the Cortex-M4 processor into their design and realize maximum system performance with lowest risk and fastest time-to-market.
The Cortex-M4 processor has been licensed by five leading MCU semiconductor companies including NXP, STMicroelectronics and Texas Instruments.
“The addition of the ARM Cortex-M4 processor to our ARM Cortex portfolio complements our Cortex-M3 and Cortex-M0 processor-based devices and enables us to provide an end to end solution to the MCU community,” said Geoff Lees, General Manager, Microcontroller Product Line, NXP Semiconductors. “The Cortex-M4 processor now enables a new class of microcontrollers to meet the high-performance, low-cost needs of the signal processing markets.”
“The Cortex-M4 processor extends the use of Cortex-M cores to applications requiring intensive mathematical computation,” said Semir Haddad, 32-bit MCU Marketing Manager of ST Microcontroller division. “A product line based on the Cortex-M4 processor will complement our line of STM32 microcontrollers, giving our customers the ability to combine the scalability of STM32 with enhanced signal processing capability.”
“The Cortex-M4 processor makes PID loops and upper level motion control work better and more reliably, enhancing a developer's ability to achieve high levels of energy conservation through efficient motor control,” said Jean Anne Booth, director of worldwide Stellaris MCU marketing, Texas Instruments Incorporated.
“It also opens up ARM MCU usage to the broad world of non-programmers using meta-language tools such as LabVIEW, and Matlab/Simulink. In addition, it allows natural and native C and C++ applications to be used, saving time and risk by using the same algorithm on both the deeply embedded system and the workstation, phone and general embedded processor.”
“ARM has included DSP functionality in our processors for some time and they have been extremely successful in the applications market, but this is the first time we have designed a processor with digital signal control capabilities for deeply embedded devices,” said Eric Schorn, Vice President of Marketing, Processor Division, ARM. “The Cortex-M4 processor has been designed to address the increasing demand for signal processing in an ever-increasing range of embedded applications including motor control, automotive, industrial automation, power management and audio applications.”
The outstanding combination of high-efficiency signal processing functionality with the unmatched low-power, low cost and ease-of-use benefits of the Cortex-M family processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets.
The Cortex-M4 processor features a single-cycle multiply-accumulate (MAC)unit, optimized single instruction multiple data (SIMD) instructions, saturating arithmetic instructions and an optional single precision Floating-Point Unit (FPU). These digital signal control features build upon the innovative technology that characterizes the ARM Cortex-M family of processors.
These features include a 32-bit core capable of 1.25DMIPS/MHz for high performance, Thumb-2 instructions for optimum code density and a Nested Vector Interrupt Controller for outstanding interrupt handling. In addition, the processor features an optional Memory Protection Unit (MPU), low cost debug/trace and integrated sleep states for increased flexibility. Embedded developers will be able to rapidly design and deliver compelling end-products with maximum functionality and the absolute minimum power and area footprint.
“The signal processing requirements of the embedded market are moving from dedicated processors toward hybrid microcontrollers. These products are capable of delivering outstanding digital signal control while providing the flexibility to efficiently perform other processing operations,” said Will Strauss, president of Forward Concepts, the premier market research firm tracking markets based on digital signal processing (DSP) technology.
“The ARM partnership will capitalize on this shift with the introduction of the Cortex-M4 processor which has all of the capabilities for optimum digital signal control operations combined with the proven low power performance of the Cortex-M family processors.”
The Cortex-M4 processor is supported by the ARM physical IP portfolio offering the widest foundry and technology support for physical implementations. This includes the Cortex-M Low Power Optimization Package for the TSMC CE018FG (180nm ULL) process for Partners targeting ultra low-power implementations.
For Partners targeting high-performance MCU class devices, ARM also provides physical IP solutions on leading foundry processes. For a target frequency of 150MHz for next generation MCU devices, ARM physical IP for the 65nm GLOBALFOUNDRIES 65LPe process enables a standard implementation of the Cortex-M4 processor within just 65K gates and a dynamic power consumption of less than 40µW/MHz. The FPU, if included, adds only 25K gates and enables an extremely powerful implementation within an industry leading area footprint.
Sophisticated development tool support for the Cortex-M4 processor is provided by the Keil MDK-ARM (Microcontroller Development Kit) which includes the industry-standard ARM compiler extended for SIMD and FPU. MDK-ARM also contains µVision4 with complete Cortex-M4 processor instruction simulation as well as target debugging with advanced trace capabilities.
In addition, the processor is supported with development tools, debuggers and RTOS from members of the ARM Connected Community, the industry’s largest ecosystem of companies aligned to provide a complete solution, from design to manufacture, for products based on the ARM architecture.
Cortex Microcontroller Software Interface Standard (CMSIS)
The Cortex-M4 processor is fully supported by the Cortex Microcontroller Software Interface Standard (CMSIS) the vendor-independent hardware abstraction layer for the Cortex-M processor series that enables consistent and simple software interfaces to the processor for peripherals and real-time operating systems.
ARM is currently expanding the CMSIS to include C Compiler support for Cortex-M4 processor extended instructions and is developing an optimized library designed to make signal processing programs easier to develop for MCU users. This library will include digital filter algorithms and general functions such as maths, trigonometric, and control functions. The digital filter algorithms are also intended for use with filter design utilities and design toolkits such as MATLAB and LabVIEW.
In addition, ARM has developed a series of Cortex-M4 hardware and software training courses to ensure licensees can efficiently integrate the Cortex-M4 processor into their design and realize maximum system performance with lowest risk and fastest time-to-market.
The Cortex-M4 processor has been licensed by five leading MCU semiconductor companies including NXP, STMicroelectronics and Texas Instruments.
“The addition of the ARM Cortex-M4 processor to our ARM Cortex portfolio complements our Cortex-M3 and Cortex-M0 processor-based devices and enables us to provide an end to end solution to the MCU community,” said Geoff Lees, General Manager, Microcontroller Product Line, NXP Semiconductors. “The Cortex-M4 processor now enables a new class of microcontrollers to meet the high-performance, low-cost needs of the signal processing markets.”
“The Cortex-M4 processor extends the use of Cortex-M cores to applications requiring intensive mathematical computation,” said Semir Haddad, 32-bit MCU Marketing Manager of ST Microcontroller division. “A product line based on the Cortex-M4 processor will complement our line of STM32 microcontrollers, giving our customers the ability to combine the scalability of STM32 with enhanced signal processing capability.”
“The Cortex-M4 processor makes PID loops and upper level motion control work better and more reliably, enhancing a developer's ability to achieve high levels of energy conservation through efficient motor control,” said Jean Anne Booth, director of worldwide Stellaris MCU marketing, Texas Instruments Incorporated.
“It also opens up ARM MCU usage to the broad world of non-programmers using meta-language tools such as LabVIEW, and Matlab/Simulink. In addition, it allows natural and native C and C++ applications to be used, saving time and risk by using the same algorithm on both the deeply embedded system and the workstation, phone and general embedded processor.”
“ARM has included DSP functionality in our processors for some time and they have been extremely successful in the applications market, but this is the first time we have designed a processor with digital signal control capabilities for deeply embedded devices,” said Eric Schorn, Vice President of Marketing, Processor Division, ARM. “The Cortex-M4 processor has been designed to address the increasing demand for signal processing in an ever-increasing range of embedded applications including motor control, automotive, industrial automation, power management and audio applications.”
GLOBALFOUNDRIES Singapore announces tender offer and consent solicitation for any and all of its 5.75pc senior notes due 2010
SINGAPORE: GLOBALFOUNDRIES Singapore Pte. Ltd. (f.k.a. Chartered Semiconductor Manufacturing Ltd announced that it has launched a cash tender offer and consent solicitation for any and all of its outstanding 5.75 percent Senior Notes due 2010 on the terms and conditions set forth in the Offer to Purchase and Consent Solicitation Statement dated February 22, 2010 and the related Letter of Transmittal and Consent.
The total consideration for the Tender Offer will be $1,021.25 per $1,000 principal amount of the 2010 Notes. The total consideration includes the tender offer consideration of $1,001.25 and a consent payment of $20.00 per $1,000 principal amount of the 2010 Notes.
The total consideration will only be paid to holders that validly tender and do not validly withdraw their tenders prior to 5:00 p.m., New York City time, on March 5, 2010 unless GLOBALFOUNDRIES Singapore chooses to extend or terminate the Tender Offer. The Tender Offer contemplates an early settlement option, so that holders whose 2010 Notes are validly tendered prior to the Consent Payment Deadline and accepted for purchase would receive payment as early as March 8, 2010.
The Tender Offer is scheduled to expire at 11:59 p.m., New York City time, on March 19, 2010, unless GLOBALFOUNDRIES Singapore chooses to extend or terminate the Tender Offer. Tendered 2010 Notes may be withdrawn and the related consents may be revoked at any time on or prior to 5:00 p.m., New York City time, on March 5, 2010, but not thereafter. Any tender of 2010 Notes prior to the Withdrawal Deadline may be validly withdrawn and the related consents may be revoked at any time prior to the Withdrawal Deadline, but not thereafter except to the extent the Company is required by law to provide additional withdrawal rights.
Holders that tender after the Consent Payment Deadline and prior to the Expiration Date will only be paid the tender offer consideration of $1,001.25 per $1,000 principal amount of the 2010 Notes tendered and accepted, and will not be entitled to receive the consent payment. In addition, GLOBALFOUNDRIES Singapore will pay accrued and unpaid interest on tendered and accepted 2010 Notes to, but not including, the day of payment for such 2010 Notes.
As part of the Tender Offer, GLOBALFOUNDRIES Singapore is soliciting consents from holders of the 2010 Notes to the adoption of certain amendments to the indenture governing the 2010 Notes, including eliminating substantially all of the restrictive covenants and certain events of default in the indenture. Holders cannot tender their 2010 Notes without delivering their consent and cannot deliver a consent without tendering their 2010 Notes.
The Tender Offer is subject to the satisfaction of certain conditions, including GLOBALFOUNDRIES Singapore’s receipt of valid tenders and consents from holders of at least a majority in aggregate principal amount of the 2010 Notes and other customary conditions.
The purpose of the Tender Offer is to acquire any and all of the outstanding 2010 Notes pursuant to the Tender Offer and thereby reduce the overall indebtedness of GLOBALFOUNDRIES Singapore. To the extent that any 2010 Notes remain outstanding following the Tender Offer, GLOBALFOUNDRIES Singapore intends to complete either a satisfaction and discharge of the indenture governing the 2010 Notes or a covenant defeasance for the remaining outstanding 2010 Notes.
The 2010 Notes are currently listed on the Singapore Exchange Securities Trading Limited. GLOBALFOUNDRIES Singapore intends to delist the 2010 Notes from the Singapore Exchange Securities Trading Limited as soon as practicable.
GLOBALFOUNDRIES Singapore has retained Credit Suisse Securities (USA) LLC to serve as dealer manager and solicitation agent for the Tender Offer. Global Bondholder Services Corporation will serve as the depositary and the information agent for the Tender Offer.
None of GLOBALFOUNDRIES Singapore, its board of directors, the dealer manager and solicitation agent, the depositary or the information agent is making any recommendation to holders as to whether to tender or refrain from tendering the 2010 Notes or as to whether holders should furnish the requested consent or withhold such consent with respect to the 2010 Notes.
The total consideration for the Tender Offer will be $1,021.25 per $1,000 principal amount of the 2010 Notes. The total consideration includes the tender offer consideration of $1,001.25 and a consent payment of $20.00 per $1,000 principal amount of the 2010 Notes.
The total consideration will only be paid to holders that validly tender and do not validly withdraw their tenders prior to 5:00 p.m., New York City time, on March 5, 2010 unless GLOBALFOUNDRIES Singapore chooses to extend or terminate the Tender Offer. The Tender Offer contemplates an early settlement option, so that holders whose 2010 Notes are validly tendered prior to the Consent Payment Deadline and accepted for purchase would receive payment as early as March 8, 2010.
The Tender Offer is scheduled to expire at 11:59 p.m., New York City time, on March 19, 2010, unless GLOBALFOUNDRIES Singapore chooses to extend or terminate the Tender Offer. Tendered 2010 Notes may be withdrawn and the related consents may be revoked at any time on or prior to 5:00 p.m., New York City time, on March 5, 2010, but not thereafter. Any tender of 2010 Notes prior to the Withdrawal Deadline may be validly withdrawn and the related consents may be revoked at any time prior to the Withdrawal Deadline, but not thereafter except to the extent the Company is required by law to provide additional withdrawal rights.
Holders that tender after the Consent Payment Deadline and prior to the Expiration Date will only be paid the tender offer consideration of $1,001.25 per $1,000 principal amount of the 2010 Notes tendered and accepted, and will not be entitled to receive the consent payment. In addition, GLOBALFOUNDRIES Singapore will pay accrued and unpaid interest on tendered and accepted 2010 Notes to, but not including, the day of payment for such 2010 Notes.
As part of the Tender Offer, GLOBALFOUNDRIES Singapore is soliciting consents from holders of the 2010 Notes to the adoption of certain amendments to the indenture governing the 2010 Notes, including eliminating substantially all of the restrictive covenants and certain events of default in the indenture. Holders cannot tender their 2010 Notes without delivering their consent and cannot deliver a consent without tendering their 2010 Notes.
The Tender Offer is subject to the satisfaction of certain conditions, including GLOBALFOUNDRIES Singapore’s receipt of valid tenders and consents from holders of at least a majority in aggregate principal amount of the 2010 Notes and other customary conditions.
The purpose of the Tender Offer is to acquire any and all of the outstanding 2010 Notes pursuant to the Tender Offer and thereby reduce the overall indebtedness of GLOBALFOUNDRIES Singapore. To the extent that any 2010 Notes remain outstanding following the Tender Offer, GLOBALFOUNDRIES Singapore intends to complete either a satisfaction and discharge of the indenture governing the 2010 Notes or a covenant defeasance for the remaining outstanding 2010 Notes.
The 2010 Notes are currently listed on the Singapore Exchange Securities Trading Limited. GLOBALFOUNDRIES Singapore intends to delist the 2010 Notes from the Singapore Exchange Securities Trading Limited as soon as practicable.
GLOBALFOUNDRIES Singapore has retained Credit Suisse Securities (USA) LLC to serve as dealer manager and solicitation agent for the Tender Offer. Global Bondholder Services Corporation will serve as the depositary and the information agent for the Tender Offer.
None of GLOBALFOUNDRIES Singapore, its board of directors, the dealer manager and solicitation agent, the depositary or the information agent is making any recommendation to holders as to whether to tender or refrain from tendering the 2010 Notes or as to whether holders should furnish the requested consent or withhold such consent with respect to the 2010 Notes.
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