SEOUL, SOUTH KOREA: Samsung Electronics Co. Ltd has commenced the industry’s first volume production of 3-bit, multi-level-cell (MLC) NAND flash chips using 30-nanometer (nm)-class process technology at the end of November.
The chips will be used in NAND flash modules accompanied by exclusive Samsung 3-bit NAND controllers to initially produce eight gigabyte (GB) micro Secure Digital (microSD) cards.
“Introducing cost-efficient, 30nm-class 3-bit technology widens our NAND memory solution base to make NAND even more enticing for increasingly diverse market applications,” said Soo-In Cho, executive vice president and general manager of the Memory Division at Samsung Electronics. “Our 3-bit NAND memory will support the development of more cost-competitive, high-density consumer electronics storage solutions,” he added.
Three-bit MLC NAND increases the efficiency of NAND data storage by 50 percent over today’s pervasive 2-bit MLC NAND chips. Samsung’s new 30nm-class 3-bit MLC NAND will provide consumers with effective NAND-based storage that can be applied to USB flash drives in addition to a range of micro SD cards.
In 2005, Samsung introduced the first 50nm-class, 16Gb MLC NAND memory device, ushering in an era of unprecedented growth for flash memory beyond the high-performance SLC (single-level-cell) market. Mass production of 30nm 3-bit NAND is expected to significantly raise the portion of NAND flash memory production devoted to high densities (32Gb and above), designed to accommodate increased video usage.
Other NAND advancements, like the introduction of asynchronous double data rate MLC NAND memory are expected to also contribute greatly to this trend.
Monday, 30 November 2009
KLA-Tencor launches ICOS WI-2250 wafer inspector
CHIBA, JAPAN: KLA-Tencor Corp., the world's leading supplier of process control and yield management solutions for the semiconductor and related industries, introduced the next addition to its wafer inspection portfolio, the ICOS( )WI-2250.
Extending KLA-Tencor's leading positions within the light-emitting diode (LED) and microelectromechanical systems (MEMS) market segments, the ICOS WI-2250 is a major breakthrough for the industry -- offering a dramatic improvement in inspection speed, compared to currently available products, allowing manufacturers to transition to larger LED and MEMS wafer sizes.
The ICOS WI-2250 system's automated optical inspection capabilities enable higher quality LED and MEMS products at increased yields. The new system will allow defect inspection of whole and diced wafers up to 200mm, with macro inspection sensitivity in the pre- and post-dice inspection (i.e., front- and back-end) of high-brightness (HB) LEDs and MEMS wafers.
"The new ICOS WI-2250 addresses our customers' pre- and post-dice decision needs by helping them overcome the challenge of removing dies that have passed probe, yet still have visible defects, preventing these defective die from entering the expensive packaging process," said Jeff Donnelly, group vice president, Growth and Emerging Markets (GEM) Group at KLA-Tencor.
"In addition, the improved, automated real-time classification and metrology capabilities of the ICOS WI-2250 are designed to reduce operator reclassification and manual metrology measurements, while improving inspection accuracy. That combination will lead to faster cycle time and improved process control, which enables manufacturing efficiency and increased yield."
Compared with similar products on the market today, the ICOS WI-2250 provides significantly higher inspection sensitivity to critical LED and MEMS process defects.
The new system also offers advanced rule-based binning (RBB) for real-time defect classification, advanced metrology capabilities, and faster throughput for inspection as a result of new inspection and data processing technology, which allows an increase in inspection speed.
This new solution works in conjunction with the Candela HBLED unpatterned wafer inspection system, to provide comprehensive, yield-improving inspection coverage to the front-end of the line, including analysis for disposition, defect reduction and excursion control.
The ICOS WI-2250 wafer inspection system has received multiple orders.
Extending KLA-Tencor's leading positions within the light-emitting diode (LED) and microelectromechanical systems (MEMS) market segments, the ICOS WI-2250 is a major breakthrough for the industry -- offering a dramatic improvement in inspection speed, compared to currently available products, allowing manufacturers to transition to larger LED and MEMS wafer sizes.
The ICOS WI-2250 system's automated optical inspection capabilities enable higher quality LED and MEMS products at increased yields. The new system will allow defect inspection of whole and diced wafers up to 200mm, with macro inspection sensitivity in the pre- and post-dice inspection (i.e., front- and back-end) of high-brightness (HB) LEDs and MEMS wafers.
"The new ICOS WI-2250 addresses our customers' pre- and post-dice decision needs by helping them overcome the challenge of removing dies that have passed probe, yet still have visible defects, preventing these defective die from entering the expensive packaging process," said Jeff Donnelly, group vice president, Growth and Emerging Markets (GEM) Group at KLA-Tencor.
"In addition, the improved, automated real-time classification and metrology capabilities of the ICOS WI-2250 are designed to reduce operator reclassification and manual metrology measurements, while improving inspection accuracy. That combination will lead to faster cycle time and improved process control, which enables manufacturing efficiency and increased yield."
Compared with similar products on the market today, the ICOS WI-2250 provides significantly higher inspection sensitivity to critical LED and MEMS process defects.
The new system also offers advanced rule-based binning (RBB) for real-time defect classification, advanced metrology capabilities, and faster throughput for inspection as a result of new inspection and data processing technology, which allows an increase in inspection speed.
This new solution works in conjunction with the Candela HBLED unpatterned wafer inspection system, to provide comprehensive, yield-improving inspection coverage to the front-end of the line, including analysis for disposition, defect reduction and excursion control.
The ICOS WI-2250 wafer inspection system has received multiple orders.
Samsung announces industry’s first mass production of 30nm-class asynchronous DDR NAND Flash
SEOUL, SOUTH KOREA: Samsung Electronics Co. Ltd has announced the industry’s first mass production of its 30-nanometer (nm) class, 32 gigabit (Gb), multi-level-cell (MLC) NAND memory with an asynchronous DDR (double data rate) interface. The company said it began shipping initial production of its DDR NAND to major OEMs at the end of November.
DDR NAND will sharply raise the read performance of mobile devices requiring high-speeds and large amounts of storage space. Samsung’s new DDR MLC NAND chip, which reads at 133 megabits per second (Mbps) would replace single data rate (SDR) MLC NAND, which has an overall read performance of 40Mbps.
“With the new DDR MLC NAND, double data rate transmission can be achieved without increasing power consumption, giving designers a lot more latitude in introducing diverse CE devices,” said Soo-In Cho, executive vice president and general manager of the Memory Division at Samsung Electronics.
He added: “Samsung’s accelerated push toward providing memory solutions at much higher speeds will enable faster introduction of high-performance mobile devices that deliver added convenience and greater value to consumers.”
Samsung’s new asynchronous DDR MLC NAND can be used in SSDs for PCs, premium SD memory cards for smartphones, and in Samsung’s proprietary moviNANDTM memory. In addition, the high-density, high-performance memory is an ideal solution for personal media players (PMPs), MP3 players and car navigation systems (CNS).
Production of the Samsung 30nm-class DDR MLC NAND comes just eight months after the company announced availability of its 30nm-class 32Gb MLC NAND.
Use of 30nm-class DDR NAND enables premium memory cards to register 60Mbps read speeds, at least a 300 percent performance gain compared to SDR NAND-based memory cards with an average 17Mbps read speed.
Mass production of asynchronous DDR MLC NAND, like the introduction of 30nm-class 3-bit MLC NAND is expected to substantially raise the portion of NAND flash production devoted to high density consumer electronics (32GB and above) to accommodate increased video sharing.
According to market research firm Gartner Dataquest, the global NAND flash memory market is forecast to be worth US$13.8 billion in 2009 and reach US$23.6 billion by 2012.
DDR NAND will sharply raise the read performance of mobile devices requiring high-speeds and large amounts of storage space. Samsung’s new DDR MLC NAND chip, which reads at 133 megabits per second (Mbps) would replace single data rate (SDR) MLC NAND, which has an overall read performance of 40Mbps.
“With the new DDR MLC NAND, double data rate transmission can be achieved without increasing power consumption, giving designers a lot more latitude in introducing diverse CE devices,” said Soo-In Cho, executive vice president and general manager of the Memory Division at Samsung Electronics.
He added: “Samsung’s accelerated push toward providing memory solutions at much higher speeds will enable faster introduction of high-performance mobile devices that deliver added convenience and greater value to consumers.”
Samsung’s new asynchronous DDR MLC NAND can be used in SSDs for PCs, premium SD memory cards for smartphones, and in Samsung’s proprietary moviNANDTM memory. In addition, the high-density, high-performance memory is an ideal solution for personal media players (PMPs), MP3 players and car navigation systems (CNS).
Production of the Samsung 30nm-class DDR MLC NAND comes just eight months after the company announced availability of its 30nm-class 32Gb MLC NAND.
Use of 30nm-class DDR NAND enables premium memory cards to register 60Mbps read speeds, at least a 300 percent performance gain compared to SDR NAND-based memory cards with an average 17Mbps read speed.
Mass production of asynchronous DDR MLC NAND, like the introduction of 30nm-class 3-bit MLC NAND is expected to substantially raise the portion of NAND flash production devoted to high density consumer electronics (32GB and above) to accommodate increased video sharing.
According to market research firm Gartner Dataquest, the global NAND flash memory market is forecast to be worth US$13.8 billion in 2009 and reach US$23.6 billion by 2012.
DiRT 2 offers exhilarating DirectX 11 gaming experience on ATI Radeon graphics cards
SUNNYVALE, USA: AMD announced that the Games for Windows Live Edition of DiRT 2 is now shipping and marks the first racing game developed from the ground up to take advantage of advanced graphics features available with Microsoft DirectX 11 and the incredible new ATI Eyefinity multi-display technology for the most engaging gaming experience yet.
With a wealth of image quality and performance enhancements supported only on new Direct X 11-capable ATI Radeon graphics cards, DiRT 2, the thrilling sequel to the award-winning Codemasters off-road racer, offers players a more realistic, immersive and exhilarating experience than ever before, and is the latest example of the benefits of AMD’s close working relationship with today’s leading game developers.
Some of the DirectX 11-based improvements gamers can enjoy, as compared to the DirectX 9-based version, include:
* Improved water effects including more realistic ripples, accurate reflections, and life-like splashes and wakes, more detailed, animated crowd models to cheer on your race, and smoother, more realistically flowing flags and cloth as a result of hardware tessellation where more polygons are generating the scene without degrading game performance.
* More accurate simulation of light and shadows as a result of Compute Shader 5.0 found in DirectX 11, allowing for complex computations without major hits on frame rates.
* Truer depiction of high dynamic range lighting at twice the color depth of the DirectX 9 version, with special effects rendered at the full screen resolution, up to four times the resolution of the DirectX 9 version.
DirectX 11-compatible hardware is currently available only from AMD. Players can take advantage of the DirectX 11 features in DiRT 2 on the ATI Radeon HD 5970, ATI Radeon HD 5870, ATI Radeon HD 5850, ATI Radeon HD 5770 or ATI Radeon HD 5750 graphics cards.
With a wealth of image quality and performance enhancements supported only on new Direct X 11-capable ATI Radeon graphics cards, DiRT 2, the thrilling sequel to the award-winning Codemasters off-road racer, offers players a more realistic, immersive and exhilarating experience than ever before, and is the latest example of the benefits of AMD’s close working relationship with today’s leading game developers.
Some of the DirectX 11-based improvements gamers can enjoy, as compared to the DirectX 9-based version, include:
* Improved water effects including more realistic ripples, accurate reflections, and life-like splashes and wakes, more detailed, animated crowd models to cheer on your race, and smoother, more realistically flowing flags and cloth as a result of hardware tessellation where more polygons are generating the scene without degrading game performance.
* More accurate simulation of light and shadows as a result of Compute Shader 5.0 found in DirectX 11, allowing for complex computations without major hits on frame rates.
* Truer depiction of high dynamic range lighting at twice the color depth of the DirectX 9 version, with special effects rendered at the full screen resolution, up to four times the resolution of the DirectX 9 version.
DirectX 11-compatible hardware is currently available only from AMD. Players can take advantage of the DirectX 11 features in DiRT 2 on the ATI Radeon HD 5970, ATI Radeon HD 5870, ATI Radeon HD 5850, ATI Radeon HD 5770 or ATI Radeon HD 5750 graphics cards.
Spansion MirrorBit Flash memory now available as Xilinx Spartan-6 FPGA configuration solution
SUNNYVALE, USA: Spansion Inc. announced that the company's MirrorBit Flash memory is now available as a verified configuration solution for the new Xilinx Spartan-6 FPGA family.
Spansion is offering a MirrorBit Multi-I/O Flash add-on module that is compatible with the Xilinx Spartan-6 evaluation and development kits, enabling designers to easily evaluate and test various configuration options. These combined solutions are available through Avnet Electronics Marketing and can be used to develop an array of consumer, infotainment, video and other cost and power-sensitive applications.
"Spansion is focused on providing customers with the right development tools, either from our own systems and software teams or through collaboration with partners, to provide enhanced customer support and greater levels of value," said Tom Eby, executive vice president, Embedded Solutions Group.
"By collaborating with Avnet and Xilinx to build a flexible, cost effective, easy-to-use system for a broad range of consumer and industrial applications, Spansion is helping designers and OEMs to innovate and quickly bring their products to market."
Spansion's MirrorBit NOR GL family is featured on Avnet's Spartan-6 LX150T FPGA development kit and the adaptor modules for Spansion's MirrorBit Multi-I/O serial Flash memory product are available for the Xilinx Spartan-6 FPGA SP601, SP605 and Avnet LX16 evaluation kits. The configuration solutions are supported in the latest Xilinx ISE® Design Suite tools, simplifying bit stream generation and Flash programming.
"Spansion Flash memory is perfectly suited for the Spartan-6 configuration solution, enabling designers to easily demonstrate standard FPGA design flows and simplify application development," said Jim Beneke, vice president of global technical marketing at Avnet Electronics Marketing. "The flexibility and high performance of MirrorBit NOR solutions, with its universal footprint, for both parallel and serial Flash, enable added flexibility and rapid prototyping at lower costs in the development process for the customer."
Spansion MirrorBit Multi-I/O SPI family features the industry's fastest serial read performance in addition to leading Multi-I/O throughput performance of up to 40MB/sec (80MHz per I/O in quad I/O mode) that enables faster boot up times using FPGA configuration data. The MirrorBit Multi-I/O SPI family includes 32-megabits (Mb), 64 Mb and 128Mb devices with all three densities shipping in volume production today.
MirrorBit NOR GL products operate at 3.0 volts (Vcc), feature a random read speed of 90-100 nanoseconds (ns) access, and offer a page read speed of 25 ns via an 8-word page buffer. The MirrorBit NOR GL products include 32 Mb - 1 Gb, with all densities shipping in volume production today.
Flash memory is an integral part of the FPGA solution, providing a software-based ability to define the way transistors are connected, enabling flexibility and fine tuning even after the device is assembled into a customer's system. Flexibility and rapid development is always a key benefit when using an FPGA.
Spansion supports flexible design as well through a Universal Footprint, with consistent packaging and pin outs across multiple densities. Designers can swap devices at any point in the design or product life cycle without impacting board design.
Beyond compatibility with the Spartan-6 family, Spansion Flash memory can also be paired easily with high-performance FPGA's from the Xilinx Virtex®-6 platform for even more demanding applications.
The configuration solution and adaptor modules are now available through Avnet.
Spansion is offering a MirrorBit Multi-I/O Flash add-on module that is compatible with the Xilinx Spartan-6 evaluation and development kits, enabling designers to easily evaluate and test various configuration options. These combined solutions are available through Avnet Electronics Marketing and can be used to develop an array of consumer, infotainment, video and other cost and power-sensitive applications.
"Spansion is focused on providing customers with the right development tools, either from our own systems and software teams or through collaboration with partners, to provide enhanced customer support and greater levels of value," said Tom Eby, executive vice president, Embedded Solutions Group.
"By collaborating with Avnet and Xilinx to build a flexible, cost effective, easy-to-use system for a broad range of consumer and industrial applications, Spansion is helping designers and OEMs to innovate and quickly bring their products to market."
Spansion's MirrorBit NOR GL family is featured on Avnet's Spartan-6 LX150T FPGA development kit and the adaptor modules for Spansion's MirrorBit Multi-I/O serial Flash memory product are available for the Xilinx Spartan-6 FPGA SP601, SP605 and Avnet LX16 evaluation kits. The configuration solutions are supported in the latest Xilinx ISE® Design Suite tools, simplifying bit stream generation and Flash programming.
"Spansion Flash memory is perfectly suited for the Spartan-6 configuration solution, enabling designers to easily demonstrate standard FPGA design flows and simplify application development," said Jim Beneke, vice president of global technical marketing at Avnet Electronics Marketing. "The flexibility and high performance of MirrorBit NOR solutions, with its universal footprint, for both parallel and serial Flash, enable added flexibility and rapid prototyping at lower costs in the development process for the customer."
Spansion MirrorBit Multi-I/O SPI family features the industry's fastest serial read performance in addition to leading Multi-I/O throughput performance of up to 40MB/sec (80MHz per I/O in quad I/O mode) that enables faster boot up times using FPGA configuration data. The MirrorBit Multi-I/O SPI family includes 32-megabits (Mb), 64 Mb and 128Mb devices with all three densities shipping in volume production today.
MirrorBit NOR GL products operate at 3.0 volts (Vcc), feature a random read speed of 90-100 nanoseconds (ns) access, and offer a page read speed of 25 ns via an 8-word page buffer. The MirrorBit NOR GL products include 32 Mb - 1 Gb, with all densities shipping in volume production today.
Flash memory is an integral part of the FPGA solution, providing a software-based ability to define the way transistors are connected, enabling flexibility and fine tuning even after the device is assembled into a customer's system. Flexibility and rapid development is always a key benefit when using an FPGA.
Spansion supports flexible design as well through a Universal Footprint, with consistent packaging and pin outs across multiple densities. Designers can swap devices at any point in the design or product life cycle without impacting board design.
Beyond compatibility with the Spartan-6 family, Spansion Flash memory can also be paired easily with high-performance FPGA's from the Xilinx Virtex®-6 platform for even more demanding applications.
The configuration solution and adaptor modules are now available through Avnet.
Applied Materials' smart emissions control solution cuts energy use, cost in semicon fabs
TOKYO, JAPAN: Applied Materials Inc. has unveiled its Applied iSYS platform, the industry’s first fully-integrated abatement and vacuum pumping solution for controlling emissions in the semiconductor fab.
Networked with an Applied process tool, the iSYS system can deliver typical annual savings in power, water and gas consumption equivalent to 200MWh of energy or 220,000 pounds of CO2 emissions, compared to currently available configurations. In addition to having environmental benefits, the iSYS system lowers the utility cost for abatement and vacuum pumping on a process tool by more than 20%.
Key to the iSYS platform’s capability to conserve resources is its unique control system that is synchronized with the wafer processing tool, sensing real-time changes in each process chamber and directing subsystems into pre-defined standby states. Utility metering sensors and software are built into every iSYS platform to enable remote monitoring of cumulative energy savings and to track progress in reaching energy sustainability targets.
“With the iSYS platform Applied is capitalizing on its unmatched equipment automation and process tool technology to create a smart solution for decreasing waste in semiconductor manufacturing,” said Charlie Pappis, vice president and general manager of Applied Global Services. “By modulating resource consumption in response to changing tool conditions, the iSYS platform can help our customers lower their operating costs and support sustainable manufacturing practices.”
The highly-compact Applied iSYS unit can be installed in less than one day and consumes 40% less floor space than non-integrated systems. Designed from the outset for maximum ease of servicing, the iSYS design consolidates major components and eliminates redundancy to greatly reduce the number of external connections while optimizing maintenance ergonomics.
By stacking lighter components above heavier ones and optimizing duct routing, technicians can quickly complete all service tasks, including pump replacement, without special equipment.
The substantial energy saving achieved by the iSYS platform was measured at Applied’s advanced Maydan Technology Center on an Applied Producer GT PECVD* system using SEMI S23 methodology. Initially launched for Applied Materials’ CVD systems, the flexible iSYS architecture can also support etch applications.
Networked with an Applied process tool, the iSYS system can deliver typical annual savings in power, water and gas consumption equivalent to 200MWh of energy or 220,000 pounds of CO2 emissions, compared to currently available configurations. In addition to having environmental benefits, the iSYS system lowers the utility cost for abatement and vacuum pumping on a process tool by more than 20%.
Key to the iSYS platform’s capability to conserve resources is its unique control system that is synchronized with the wafer processing tool, sensing real-time changes in each process chamber and directing subsystems into pre-defined standby states. Utility metering sensors and software are built into every iSYS platform to enable remote monitoring of cumulative energy savings and to track progress in reaching energy sustainability targets.
“With the iSYS platform Applied is capitalizing on its unmatched equipment automation and process tool technology to create a smart solution for decreasing waste in semiconductor manufacturing,” said Charlie Pappis, vice president and general manager of Applied Global Services. “By modulating resource consumption in response to changing tool conditions, the iSYS platform can help our customers lower their operating costs and support sustainable manufacturing practices.”
The highly-compact Applied iSYS unit can be installed in less than one day and consumes 40% less floor space than non-integrated systems. Designed from the outset for maximum ease of servicing, the iSYS design consolidates major components and eliminates redundancy to greatly reduce the number of external connections while optimizing maintenance ergonomics.
By stacking lighter components above heavier ones and optimizing duct routing, technicians can quickly complete all service tasks, including pump replacement, without special equipment.
The substantial energy saving achieved by the iSYS platform was measured at Applied’s advanced Maydan Technology Center on an Applied Producer GT PECVD* system using SEMI S23 methodology. Initially launched for Applied Materials’ CVD systems, the flexible iSYS architecture can also support etch applications.
Broadcom to acquire Dune Networks
IRVINE, USA: Broadcom Corp. announced that it has signed a definitive agreement to acquire Dune Networks, a privately-held company that develops switch fabric solutions for data center networking equipment.
Data centers are scaling to provide significantly more bandwidth to meet the requirements of cloud computing, where computing resources, products and services, such as Software as a Service (SaaS), can be delivered real-time over the Internet. Dune Networks has developed a scalable chipset that supports bandwidth speeds of up to 100Gbps per port and can connect more than ten thousand servers (ports) in a single deployment.
"Dune's massively scalable interconnect fabric, combined with our Ethernet products, augments our portfolio of solutions for data center networking equipment," said Martin Lund, Vice President and General Manager, Broadcom's Network Switching line of business.
"This technology is particularly well suited to meet the emerging requirements for cloud computing networks at a large scale, and will enable us to address new market applications for Ethernet in the data center."
"Dune Networks' distributed connection fabric is a complement to Broadcom's existing product suite," said Eyal Dagan, Chief Executive Officer, Dune Networks. "Our joint customers will be able to bring to market low cost, high performance data center switching that will enable end users to build next-generation cloud computing networks."
In connection with the acquisition, Broadcom expects to pay approximately $178 million, net of cash assumed from Dune Networks, to acquire all of the outstanding shares of capital stock and other rights of Dune Networks.
The purchase price will be paid in cash, except that a portion of such purchase price attributable to unvested employee stock options will be paid in Broadcom restricted stock units. A portion of the cash consideration payable to the stockholders will be placed into escrow pursuant to the terms of the acquisition agreement.
Excluding any purchase accounting related adjustments and fair value measurements, Broadcom expects the acquisition of Dune Networks will be neutral to slightly accretive to earnings per share in 2010. The boards of directors of the two companies have approved the merger. The closing, which is expected to occur by the end of Broadcom's first quarter ending March 31, 2010, remains subject to customary closing conditions.
Data centers are scaling to provide significantly more bandwidth to meet the requirements of cloud computing, where computing resources, products and services, such as Software as a Service (SaaS), can be delivered real-time over the Internet. Dune Networks has developed a scalable chipset that supports bandwidth speeds of up to 100Gbps per port and can connect more than ten thousand servers (ports) in a single deployment.
"Dune's massively scalable interconnect fabric, combined with our Ethernet products, augments our portfolio of solutions for data center networking equipment," said Martin Lund, Vice President and General Manager, Broadcom's Network Switching line of business.
"This technology is particularly well suited to meet the emerging requirements for cloud computing networks at a large scale, and will enable us to address new market applications for Ethernet in the data center."
"Dune Networks' distributed connection fabric is a complement to Broadcom's existing product suite," said Eyal Dagan, Chief Executive Officer, Dune Networks. "Our joint customers will be able to bring to market low cost, high performance data center switching that will enable end users to build next-generation cloud computing networks."
In connection with the acquisition, Broadcom expects to pay approximately $178 million, net of cash assumed from Dune Networks, to acquire all of the outstanding shares of capital stock and other rights of Dune Networks.
The purchase price will be paid in cash, except that a portion of such purchase price attributable to unvested employee stock options will be paid in Broadcom restricted stock units. A portion of the cash consideration payable to the stockholders will be placed into escrow pursuant to the terms of the acquisition agreement.
Excluding any purchase accounting related adjustments and fair value measurements, Broadcom expects the acquisition of Dune Networks will be neutral to slightly accretive to earnings per share in 2010. The boards of directors of the two companies have approved the merger. The closing, which is expected to occur by the end of Broadcom's first quarter ending March 31, 2010, remains subject to customary closing conditions.
Inphi files lawsuit against Netlist Inc.
WESTLAKE VILLAGE, USA: Inphi Corp., a high-speed analog semiconductor company and leading innovator in memory standards, has filed a patent infringement lawsuit against Netlist Inc. in the United States District Court for the Central District of California.
Inphi’s lawsuit alleges that Netlist’s DDR3 Registered memory modules, including their recently announced HyperCloud, infringe on the following Inphi U.S. Patents: No: 7,307,863 and 7,479,799. The patents relate to memory interface technologies used in enterprise server and storage applications.
Inphi is a high-speed analog semiconductor company providing leading-edge interface components that operate at critical interfaces within cloud computing environments, addressing the bandwidth, capacity and power issues faced by data centers and 40G/100G networks.
By leveraging its core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets it serves. Inphi’s more than 150 analog components push the boundaries of existing server, storage and broadband networking applications while paving the way for new ones.
Inphi’s lawsuit alleges that Netlist’s DDR3 Registered memory modules, including their recently announced HyperCloud, infringe on the following Inphi U.S. Patents: No: 7,307,863 and 7,479,799. The patents relate to memory interface technologies used in enterprise server and storage applications.
Inphi is a high-speed analog semiconductor company providing leading-edge interface components that operate at critical interfaces within cloud computing environments, addressing the bandwidth, capacity and power issues faced by data centers and 40G/100G networks.
By leveraging its core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets it serves. Inphi’s more than 150 analog components push the boundaries of existing server, storage and broadband networking applications while paving the way for new ones.
Applied Materials releases industry’s most advanced, productive CMP platform – the Reflexion GT
TOKYO, JAPAN: Applied Materials Inc. has raised CMP technology to a new level while lowering system cost of ownership (CoO) with the launch of its Applied Reflexion GT system for advanced metal CMP applications.
The system’s novel, dual-wafer design sets new benchmarks in CMP performance and productivity, delivering superior profile control and 60% higher throughput than competing systems. The Reflexion GT also dramatically cuts consumables cost, requiring up to 30% less slurry and processing twice as many wafers per polishing pad.
“Today’s copper-based logic and memory devices have more copper interconnect layers, requiring faster CMP processing and more efficient use of consumables,” said Lakshmanan Karuppiah, general manager of Applied’s CMP business unit.
“Like Applied’s highly-successful Producer GT CVD platform, the Reflexion GT system is another dream machine for customers –- combining innovations in CMP technology with dual-wafer processing to achieve best-of-breed performance. In addition to its high speed throughput, this new architecture allows customers to realize substantial savings in the cost of consumables, which typically comprises 70% of the total cost per wafer.”
Key to the Reflexion GT system’s benchmark performance is its dual mode architecture, enabling two wafers to be processed simultaneously on each platen using independently-controlled Titan Contour polishing heads. After polishing is complete, a parallel-path, clean module featuring Applied’s proven Marangoni vapor drying delivers highly-effective, water mark-free wafer cleaning.
The system’s proprietary, real-time profile and endpoint control technologies provide industry-leading, wafer-to-wafer uniformity.
The Reflexion GT system is available now for copper interconnect planarization and has demonstrated extendibility to tungsten applications. This innovative system adds to Applied’s decade of leadership in CMP technology, with more than 2,700 systems at customer sites worldwide.
The system’s novel, dual-wafer design sets new benchmarks in CMP performance and productivity, delivering superior profile control and 60% higher throughput than competing systems. The Reflexion GT also dramatically cuts consumables cost, requiring up to 30% less slurry and processing twice as many wafers per polishing pad.
“Today’s copper-based logic and memory devices have more copper interconnect layers, requiring faster CMP processing and more efficient use of consumables,” said Lakshmanan Karuppiah, general manager of Applied’s CMP business unit.
“Like Applied’s highly-successful Producer GT CVD platform, the Reflexion GT system is another dream machine for customers –- combining innovations in CMP technology with dual-wafer processing to achieve best-of-breed performance. In addition to its high speed throughput, this new architecture allows customers to realize substantial savings in the cost of consumables, which typically comprises 70% of the total cost per wafer.”
Key to the Reflexion GT system’s benchmark performance is its dual mode architecture, enabling two wafers to be processed simultaneously on each platen using independently-controlled Titan Contour polishing heads. After polishing is complete, a parallel-path, clean module featuring Applied’s proven Marangoni vapor drying delivers highly-effective, water mark-free wafer cleaning.
The system’s proprietary, real-time profile and endpoint control technologies provide industry-leading, wafer-to-wafer uniformity.
The Reflexion GT system is available now for copper interconnect planarization and has demonstrated extendibility to tungsten applications. This innovative system adds to Applied’s decade of leadership in CMP technology, with more than 2,700 systems at customer sites worldwide.
Applied Materials solves critical transistor scaling challenge with new millisecond anneal system
TOKYO, JAPAN: Applied Materials Inc., the leader in rapid thermal processing (RTP), announced its new Applied Vantage Astra millisecond anneal system, an important breakthrough in transistor fabrication that enables faster, lower power consumption devices.
Targeted for creating the sensitive nickel silicide (NiSi) transistor contact layers in 45nm and beyond logic chips, this state-of-the-art laser-based system can enhance drive current and reduce gate leakage by an order of magnitude, helping customers to significantly increase device performance and yield.
The Vantage Astra’s compact design delivers more than twice the wafer output of competing systems and the lowest available cost of ownership (CoO).
“Applied’s millisecond anneal technology will enable us to successfully fabricate our customers’ most advanced device designs,” said Dr. Shang-Yi Chiang, senior vice president, Taiwan Semiconductor Manufacturing Company Limited (TSMC). “The Vantage Astra system is now TSMC’s tool of record for NiSi annealing in our 28nm logic processes.”
“We’re building on Applied’s decade of leadership in single-wafer thermal processing to help our customers address critical transistor scaling challenges,” said Steve Ghanayem, corporate vice president and general manager of Applied’s Front End Products business unit. “The Vantage Astra system’s novel, laser-based architecture sets new standards for production-worthiness and provides a compelling value proposition for advanced anneal applications.”
Key to the Vantage Astra system’s groundbreaking performance is its novel dynamic surface annealing (DSA) technology, an innovative thermal processing method that abruptly raises the surface temperature of the wafer locally to modify material properties at the atomic level.
In less than a millisecond, the Astra system can heat the wafer to over 1,000°C from a low, sub-200°C starting point. This unique capability is essential for customers to create optimum-quality NiSi films without any detrimental effect on the wafer.
The Vantage platform can be configured with two Astra millisecond anneal chambers or one Astra chamber combined with a conventional RTP RadiancePlus or RadOx chamber. This unique flexibility allows customers to perform all thermal processing steps – millisecond, spike and soak anneals, plus multiple nitridation and oxidation applications –- on the same production-proven Vantage platform.
Targeted for creating the sensitive nickel silicide (NiSi) transistor contact layers in 45nm and beyond logic chips, this state-of-the-art laser-based system can enhance drive current and reduce gate leakage by an order of magnitude, helping customers to significantly increase device performance and yield.
The Vantage Astra’s compact design delivers more than twice the wafer output of competing systems and the lowest available cost of ownership (CoO).
“Applied’s millisecond anneal technology will enable us to successfully fabricate our customers’ most advanced device designs,” said Dr. Shang-Yi Chiang, senior vice president, Taiwan Semiconductor Manufacturing Company Limited (TSMC). “The Vantage Astra system is now TSMC’s tool of record for NiSi annealing in our 28nm logic processes.”
“We’re building on Applied’s decade of leadership in single-wafer thermal processing to help our customers address critical transistor scaling challenges,” said Steve Ghanayem, corporate vice president and general manager of Applied’s Front End Products business unit. “The Vantage Astra system’s novel, laser-based architecture sets new standards for production-worthiness and provides a compelling value proposition for advanced anneal applications.”
Key to the Vantage Astra system’s groundbreaking performance is its novel dynamic surface annealing (DSA) technology, an innovative thermal processing method that abruptly raises the surface temperature of the wafer locally to modify material properties at the atomic level.
In less than a millisecond, the Astra system can heat the wafer to over 1,000°C from a low, sub-200°C starting point. This unique capability is essential for customers to create optimum-quality NiSi films without any detrimental effect on the wafer.
The Vantage platform can be configured with two Astra millisecond anneal chambers or one Astra chamber combined with a conventional RTP RadiancePlus or RadOx chamber. This unique flexibility allows customers to perform all thermal processing steps – millisecond, spike and soak anneals, plus multiple nitridation and oxidation applications –- on the same production-proven Vantage platform.
Altera updates Q4 guidance sales expectations move upward
SAN JOSE, USA: Altera Corp. announced that, based on quarter-to-date results and the company's outlook for the remainder of the quarter, the company now expects sales for the fourth quarter to be 15 percent to 18 percent above third quarter levels. Previous guidance was for sales growth of 6 percent to 10 percent.
The company expects all four of its vertical markets to be up sequentially in the fourth quarter reflecting a strong new product cycle as well as improving end market trends and customer desire for appropriate inventory to support sales levels.
Sales to wireline and wireless telecommunications equipment manufacturers will likely be the largest contributor to fourth quarter growth as demand for Chinese and Indian deployments has continued to improve.
The company will announce fourth quarter results after the market close on January 26, 2010.
The company expects all four of its vertical markets to be up sequentially in the fourth quarter reflecting a strong new product cycle as well as improving end market trends and customer desire for appropriate inventory to support sales levels.
Sales to wireline and wireless telecommunications equipment manufacturers will likely be the largest contributor to fourth quarter growth as demand for Chinese and Indian deployments has continued to improve.
The company will announce fourth quarter results after the market close on January 26, 2010.
Advantest sponsors annual Global Semiconductor Association (GSA) awards dinner
SANTA CLARA, USA: Advantest Corp., the world's leading supplier of semiconductor test equipment, announced its sponsorship of the GSA Awards Dinner Celebration to be held on Thursday, December 10, 2009 at the Santa Clara Convention Center in Santa Clara, Calif.
This premier annual event recognizes individuals and companies that have demonstrated excellence through their vision, strategy and execution, and honors achievements in several categories ranging from outstanding leadership to financial accomplishments.
At the dinner, Dr. Art de Geus, chairman and chief executive officer of Synopsys, Inc. will receive the Dr. Morris Chang Exemplary Leadership Award in recognition of his contributions to the semiconductor industry.
Supporting the evening's theme of “Innovation: A Blueprint for Global Change,” will be keynote speaker Larry Kudlow, host of CNBC’s primetime “The Kudlow Report” and co-host of CNBC’s “The Call.” A nationally syndicated columnist, he is also a contributing editor of National Review magazine, as well as a columnist and economics editor for National Review Online. He is the author of "American Abundance: The New Economic and Moral Prosperity," published by Forbes in January 1998.
“Advantest is proud to be a sponsor of this year’s GSA Awards Dinner and an on-going member of the Global Semiconductor Alliance,” commented R. Keith Lee, president and CEO of Advantest America Inc.
“GSA is a vital organization which continues to have a significant impact on the industry. It plays a critical role in the development, growth and profitability of the global semiconductor industry by promoting innovation through collaboration. We applaud Dr. de Geus and all those who will receive recognition at the event,” he continued.
This premier annual event recognizes individuals and companies that have demonstrated excellence through their vision, strategy and execution, and honors achievements in several categories ranging from outstanding leadership to financial accomplishments.
At the dinner, Dr. Art de Geus, chairman and chief executive officer of Synopsys, Inc. will receive the Dr. Morris Chang Exemplary Leadership Award in recognition of his contributions to the semiconductor industry.
Supporting the evening's theme of “Innovation: A Blueprint for Global Change,” will be keynote speaker Larry Kudlow, host of CNBC’s primetime “The Kudlow Report” and co-host of CNBC’s “The Call.” A nationally syndicated columnist, he is also a contributing editor of National Review magazine, as well as a columnist and economics editor for National Review Online. He is the author of "American Abundance: The New Economic and Moral Prosperity," published by Forbes in January 1998.
“Advantest is proud to be a sponsor of this year’s GSA Awards Dinner and an on-going member of the Global Semiconductor Alliance,” commented R. Keith Lee, president and CEO of Advantest America Inc.
“GSA is a vital organization which continues to have a significant impact on the industry. It plays a critical role in the development, growth and profitability of the global semiconductor industry by promoting innovation through collaboration. We applaud Dr. de Geus and all those who will receive recognition at the event,” he continued.
ISSI 512Mb High Speed DDR2 SDRAM for automotive, networking, telecom and industrial apps
SAN JOSE, USA: Integrated Silicon Solution Inc., a leader in advanced memory solutions, has added the 512Mb density to its family of DDR2 SDRAMs.
The IS43DR16320B (512Mb) device is organized as 32Mx16 and is available in an 84 ball BGA package. The continued expansion of the DDR2 SDRAM product family adds to ISSI's already extensive offering of DRAMs.
The IS43DR16320B is available with clock speeds up to 400MHz (DDR2-800), providing a data transfer rate of 3 gigabytes/sec in 32 bit systems. In addition to the 512Mb device, ISSI offers 256Mb DDR2 devices, with both densities available in commercial, industrial and automotive grades.
The 256Mb density devices include 8Mx32 and 16Mx16 organizations. In Q1 of 2010, ISSI will add 1Gb devices organized as 64Mx16 and 128Mx8 as well as x8 versions of the 256Mb and 512Mb devices. The DDR2 DRAM product family operates from a single supply voltage of 1.8V.
"DDR2 SDRAMs are being introduced in order to support the needs of our strategic customer base. Expanding our DDR2 SDRAM product offering is part of ISSI's long-term commitment to support a complete range of high-quality DRAMs using leading-edge technology," said Ron Kalakuntla, ISSI Vice President of Marketing.
"We will continue to invest in our DRAM product line to include a variety of interfaces, densities, organizations, and temperature ranges targeted for Automotive, Networking, Telecom, and Digital Consumer Applications."
Key applications in networking and telecom include access nodes, aggregation nodes, VoIP, switches, routers, and packet optical transport. Automotive applications are infotainment and telematics. Other applications include network storage, set-top boxes, DVRs, and others.
In addition to SDR, mobile SDR/DDR, DDR, and DDR2 SDRAMs, ISSI also offers a complete line of both asynchronous and synchronous SRAM with densities from 64Kb to 72Mb. ISSI also has a range of Known Good Die (KGD) memories in its portfolio.
For quantities of 10,000, the IS43DR16320B, in an 84 ball BGA package with a commercial operating temperature range of 0 degrees C to 85 degrees C(Tcase), is priced at $5.00. Samples are available now with volume production shipments beginning in Q1, 2010. Samples of the automotive version, the IS46DR16320B, are also available.
The IS43DR16320B (512Mb) device is organized as 32Mx16 and is available in an 84 ball BGA package. The continued expansion of the DDR2 SDRAM product family adds to ISSI's already extensive offering of DRAMs.
The IS43DR16320B is available with clock speeds up to 400MHz (DDR2-800), providing a data transfer rate of 3 gigabytes/sec in 32 bit systems. In addition to the 512Mb device, ISSI offers 256Mb DDR2 devices, with both densities available in commercial, industrial and automotive grades.
The 256Mb density devices include 8Mx32 and 16Mx16 organizations. In Q1 of 2010, ISSI will add 1Gb devices organized as 64Mx16 and 128Mx8 as well as x8 versions of the 256Mb and 512Mb devices. The DDR2 DRAM product family operates from a single supply voltage of 1.8V.
"DDR2 SDRAMs are being introduced in order to support the needs of our strategic customer base. Expanding our DDR2 SDRAM product offering is part of ISSI's long-term commitment to support a complete range of high-quality DRAMs using leading-edge technology," said Ron Kalakuntla, ISSI Vice President of Marketing.
"We will continue to invest in our DRAM product line to include a variety of interfaces, densities, organizations, and temperature ranges targeted for Automotive, Networking, Telecom, and Digital Consumer Applications."
Key applications in networking and telecom include access nodes, aggregation nodes, VoIP, switches, routers, and packet optical transport. Automotive applications are infotainment and telematics. Other applications include network storage, set-top boxes, DVRs, and others.
In addition to SDR, mobile SDR/DDR, DDR, and DDR2 SDRAMs, ISSI also offers a complete line of both asynchronous and synchronous SRAM with densities from 64Kb to 72Mb. ISSI also has a range of Known Good Die (KGD) memories in its portfolio.
For quantities of 10,000, the IS43DR16320B, in an 84 ball BGA package with a commercial operating temperature range of 0 degrees C to 85 degrees C(Tcase), is priced at $5.00. Samples are available now with volume production shipments beginning in Q1, 2010. Samples of the automotive version, the IS46DR16320B, are also available.
Lattice ships 25 millionth MachXO programmable logic device
HILLSBORO, USA: Lattice Semiconductor Corp. announced that it has shipped over 25 million MachXO PLDs. Broadly adopted in a wide range of high volume, cost sensitive applications, customers worldwide are using the MachXO PLD family due to its unparalleled ease-of-use, flexibility, system integration and price.
"We use MachXO PLDs in our high volume POS terminals as they deliver superior system integration benefits," said Qiaoying Tu, technical director of digital equipment at Fujian Newland Computer. "Lattice has done an exceptional job in shipping MachXO PLDs to us on schedule and continues to help drive down our development costs by enabling us to get to market quickly and offer our customers a competitive solution at affordable price points."
The MachXO PLD family's system integration benefits have fueled its increasing adoption in a wide range of low-density applications that require general purpose I/O expansion, interface bridging and power-up management functions.
The MachXO PLD family offers customers an "All-in-One-PLD" by providing distributed and embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFR™ technology) and a low power sleep mode, all in a single device.
"The overwhelming customer acceptance of MachXO PLDs confirms that we are meeting our customers' expectations for an easy-to-use, cost-effective, flexible and integrated solution that provides a compelling alternative to high risk ASICs and inflexible ASSPs," said Chris Fanning, Lattice Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions.
"Since their introduction, MachXO PLD sales have ramped up very quickly in a variety of end markets including communications, consumer, computing, industrial and medical, and the MachXO device continues to be one of Lattice's fastest growing products."
Reference Designs and Easy-to-Use Development Kits
In order to accelerate development time, 28 popular reference designs and the easy-to-use MachXO Mini Development Kit are available for prototyping cost sensitive low-density applications.
Using the preloaded mini system-on-chip (mini SoC) design provided with the development kit, designers can now test within minutes I2C, SPI and UART interfaces in addition to the 8-bit LatticeMico8 microcontroller and low power sleep mode functionality. Designers can then build their own designs using the free downloadable reference design source codes, implementing these features in less than an hour.
Targeted for system control applications, the MachXO Control Development Kit enables designers to rapidly prototype typical board control functions such as temperature and current monitoring, power supply sequencing, fault logging, reset distribution and fan control used in system control designs.
"We use MachXO PLDs in our high volume POS terminals as they deliver superior system integration benefits," said Qiaoying Tu, technical director of digital equipment at Fujian Newland Computer. "Lattice has done an exceptional job in shipping MachXO PLDs to us on schedule and continues to help drive down our development costs by enabling us to get to market quickly and offer our customers a competitive solution at affordable price points."
The MachXO PLD family's system integration benefits have fueled its increasing adoption in a wide range of low-density applications that require general purpose I/O expansion, interface bridging and power-up management functions.
The MachXO PLD family offers customers an "All-in-One-PLD" by providing distributed and embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFR™ technology) and a low power sleep mode, all in a single device.
"The overwhelming customer acceptance of MachXO PLDs confirms that we are meeting our customers' expectations for an easy-to-use, cost-effective, flexible and integrated solution that provides a compelling alternative to high risk ASICs and inflexible ASSPs," said Chris Fanning, Lattice Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions.
"Since their introduction, MachXO PLD sales have ramped up very quickly in a variety of end markets including communications, consumer, computing, industrial and medical, and the MachXO device continues to be one of Lattice's fastest growing products."
Reference Designs and Easy-to-Use Development Kits
In order to accelerate development time, 28 popular reference designs and the easy-to-use MachXO Mini Development Kit are available for prototyping cost sensitive low-density applications.
Using the preloaded mini system-on-chip (mini SoC) design provided with the development kit, designers can now test within minutes I2C, SPI and UART interfaces in addition to the 8-bit LatticeMico8 microcontroller and low power sleep mode functionality. Designers can then build their own designs using the free downloadable reference design source codes, implementing these features in less than an hour.
Targeted for system control applications, the MachXO Control Development Kit enables designers to rapidly prototype typical board control functions such as temperature and current monitoring, power supply sequencing, fault logging, reset distribution and fan control used in system control designs.
DALSA intros PC-based, real-time digital image processor board for x-ray imaging
CHICAGO, USA: DALSA, a leader in digital imaging technology, announced the introduction of its XRI-1600 digital image processor, which is ideal for X-ray imaging applications. At RSNA 2009, the annual meeting of the Radiological Society of North America held at McCormick Place in Chicago, DALSA will be demonstrating the XRI-1600 at Booth #7117 (North Building, Hall B) from Nov. 29-Dec. 4, 2009.
Specifically engineered for demanding X-ray instrumentation and radioscopy, the XRI-1600 is capable of handling a wide range of resolutions, pixel depths and frame rates.
High quality diagnostic pictures with DALSA's image processing engine
The XRI-1600 image processor is able to generate such high quality diagnostic pictures due to the incorporation of DALSA's Image Processing Engine (IPE). The IPE is specially designed for X-ray imaging applications and performs real-time digital image processing in three dynamic stages.
These stages are: input image conditioning; motion compensated noise reduction; and output image conditioning. In the first stage, the IPE is capable of performing shading correction, lens correction, and image realignment as required, without sacrificing system performance.
In the second stage, the XRI-1600 features a user configurable, motion-compensated noise reduction algorithm that is optimized for both static and dynamic images. The third stage enables image rotation and/or flip, along with image enhancement and masking.
Inder Kohli, Product Line Manager for DALSA, states: "DALSA's XRI-1600 performs adaptive image processing through the Image Processing Engine to reduce noise in both still and dynamic images and greatly improve image quality and image contrast. This is a key requirement of X-ray and radioscopy applications which typically exhibit low contrast, high-noise, and contain motion artifacts."
Specifically engineered for demanding X-ray instrumentation and radioscopy, the XRI-1600 is capable of handling a wide range of resolutions, pixel depths and frame rates.
High quality diagnostic pictures with DALSA's image processing engine
The XRI-1600 image processor is able to generate such high quality diagnostic pictures due to the incorporation of DALSA's Image Processing Engine (IPE). The IPE is specially designed for X-ray imaging applications and performs real-time digital image processing in three dynamic stages.
These stages are: input image conditioning; motion compensated noise reduction; and output image conditioning. In the first stage, the IPE is capable of performing shading correction, lens correction, and image realignment as required, without sacrificing system performance.
In the second stage, the XRI-1600 features a user configurable, motion-compensated noise reduction algorithm that is optimized for both static and dynamic images. The third stage enables image rotation and/or flip, along with image enhancement and masking.
Inder Kohli, Product Line Manager for DALSA, states: "DALSA's XRI-1600 performs adaptive image processing through the Image Processing Engine to reduce noise in both still and dynamic images and greatly improve image quality and image contrast. This is a key requirement of X-ray and radioscopy applications which typically exhibit low contrast, high-noise, and contain motion artifacts."
ANADIGICS announces industry's first family of gateway splitters featuring up to eight RF outputs
TOKYO, JAPAN: ANADIGICS Inc. has launched the industry's first family of gateway splitters that provide up to eight RF outputs. These additional RF outputs are new to ANADIGICS's APS3600 splitter family targeted for use in home gateways which incorporate multiple tuner architectures.
ANADIGICS new five-way splitter, the APS3625, incorporates a by-pass function to enable cable supported voice phones to function even in the event of a power loss. This family of splitters also offers exceptional linearity over the cable spectrum and low return loss, thus delivering enhanced image and sound quality in a multitude of applications.
The new family of gateway splitters offers several benefits to equipment manufacturers, service providers and consumers. Equipment manufacturers benefit from integrated active solutions that have high linearity and low noise which does not degrade the signal integrity. Service providers can benefit from lower equipment costs since the box size is potentially smaller due to fewer components than traditional passive designs.
Consumers with networked entertainment devices can now enjoy the features of their primary STB or DVR, from any room within the house, resulting in an improved user experience. Businesses such as hotels can expand their TV services to more than 15 different hotel rooms using equipment containing these active splitter devices.
"The market for centralized gateways is beginning to multiply as there is an increasing need to connect applications such as a DVR, TV, and digital phones across a single home network to provide enhanced features to end-users," stated Ray Aubert, Sr. Product Marketing Manager, ANADIGICS.
"ANADIGICS has been innovating in CATV for many years, delivering some of the industry's most popular splitters and integrated tuners for the cable set-top box market. With the tremendous growth in demand for multimedia applications in business and at home, we continue to innovate, delivering industry-firsts, such as the APS3600 gateway splitters, which are highly integrated and deliver strong signal performance, high quality outputs and added functionality to meet current and future market requirements."
ANADIGICS new five-way splitter, the APS3625, incorporates a by-pass function to enable cable supported voice phones to function even in the event of a power loss. This family of splitters also offers exceptional linearity over the cable spectrum and low return loss, thus delivering enhanced image and sound quality in a multitude of applications.
The new family of gateway splitters offers several benefits to equipment manufacturers, service providers and consumers. Equipment manufacturers benefit from integrated active solutions that have high linearity and low noise which does not degrade the signal integrity. Service providers can benefit from lower equipment costs since the box size is potentially smaller due to fewer components than traditional passive designs.
Consumers with networked entertainment devices can now enjoy the features of their primary STB or DVR, from any room within the house, resulting in an improved user experience. Businesses such as hotels can expand their TV services to more than 15 different hotel rooms using equipment containing these active splitter devices.
"The market for centralized gateways is beginning to multiply as there is an increasing need to connect applications such as a DVR, TV, and digital phones across a single home network to provide enhanced features to end-users," stated Ray Aubert, Sr. Product Marketing Manager, ANADIGICS.
"ANADIGICS has been innovating in CATV for many years, delivering some of the industry's most popular splitters and integrated tuners for the cable set-top box market. With the tremendous growth in demand for multimedia applications in business and at home, we continue to innovate, delivering industry-firsts, such as the APS3600 gateway splitters, which are highly integrated and deliver strong signal performance, high quality outputs and added functionality to meet current and future market requirements."
Zarlink wireless radio solution in new camera capsule targeting colon cancer
OTTAWA, CANADA: Zarlink Semiconductor announced that its custom RF (radio frequency) integrated circuit is being used in Given Imaging's new PillCam COLON 2 camera capsule for wireless examination of the colon. The new camera capsule provides a patient-friendly alternative for visualizing the colon.
Given Imaging launched this product at the recent GASTRO 2009 meeting in London and plans to begin marketing PillCam COLON 2 in Europe in 2010. (PillCam COLON 2 is not approved for use in the USA.)
PillCam COLON 2 is a smooth, plastic capsule which can be easily swallowed by the patient without requiring sedation, intubation, air insufflation, hospitalization or radiation. The capsule contains tiny cameras at each end, a light source and Zarlink's ultra-low power RF transceiver.
Zarlink's RF chip transmits images from the PillCam COLON 2 to an external data recorder as the vitamin-sized capsule passes naturally through the patient's colon. Zarlink's RF technology is in use in Given Imaging's PillCam SB video capsules for visualizing the small bowel.
"The evolution of Given Imaging's PillCam products highlights the increasing opportunity for our radio technologies in new and emerging wireless medical devices and therapies," said Steve Swift, Senior Vice President and General Manager of Zarlink's Medical Products group.
According to the American Cancer Society, colorectal cancer is the third most common cancer diagnosis and the second-leading cause of death from cancer for both men and women in the United States. About 150,000 new cases of colorectal cancer will be diagnosed this year, with the disease expected to cause about 50,000 deaths.
The Canadian Colorectal Cancer Association estimates that 22,000 Canadians will be diagnosed with colorectal cancer and 9,100 will die from it this year. Colorectal screening can result in the detection and removal of polyps before they become cancerous, as well as discover the disease at its earliest stages.
"Zarlink's wireless technology has been a key component as we have developed our successful range of PillCam products for wireless endoscopy. Our new PillCam COLON 2 is a patient-friendly capsule endoscope that may complement traditional procedures to visualize the colon in patients who are unwilling or unable to undergo colonoscopy," said Kevin Rubey, Chief Operations Officer, Given Imaging.
Given Imaging launched this product at the recent GASTRO 2009 meeting in London and plans to begin marketing PillCam COLON 2 in Europe in 2010. (PillCam COLON 2 is not approved for use in the USA.)
PillCam COLON 2 is a smooth, plastic capsule which can be easily swallowed by the patient without requiring sedation, intubation, air insufflation, hospitalization or radiation. The capsule contains tiny cameras at each end, a light source and Zarlink's ultra-low power RF transceiver.
Zarlink's RF chip transmits images from the PillCam COLON 2 to an external data recorder as the vitamin-sized capsule passes naturally through the patient's colon. Zarlink's RF technology is in use in Given Imaging's PillCam SB video capsules for visualizing the small bowel.
"The evolution of Given Imaging's PillCam products highlights the increasing opportunity for our radio technologies in new and emerging wireless medical devices and therapies," said Steve Swift, Senior Vice President and General Manager of Zarlink's Medical Products group.
According to the American Cancer Society, colorectal cancer is the third most common cancer diagnosis and the second-leading cause of death from cancer for both men and women in the United States. About 150,000 new cases of colorectal cancer will be diagnosed this year, with the disease expected to cause about 50,000 deaths.
The Canadian Colorectal Cancer Association estimates that 22,000 Canadians will be diagnosed with colorectal cancer and 9,100 will die from it this year. Colorectal screening can result in the detection and removal of polyps before they become cancerous, as well as discover the disease at its earliest stages.
"Zarlink's wireless technology has been a key component as we have developed our successful range of PillCam products for wireless endoscopy. Our new PillCam COLON 2 is a patient-friendly capsule endoscope that may complement traditional procedures to visualize the colon in patients who are unwilling or unable to undergo colonoscopy," said Kevin Rubey, Chief Operations Officer, Given Imaging.
STATS ChipPAC ramps eWLB Technology to high volume production
SINGAPORE & USA: STATS ChipPAC Ltd, a leading semiconductor test and advanced packaging service provider, has ramped first generation embedded Wafer-Level Ball Grid Array (eWLB) technology to high volume production.
The eWLB technology provides solutions for semiconductor devices requiring a higher integration level and a greater number of external contacts. Using a combination of traditional ‘front-end’ and ‘back-end’ semiconductor manufacturing techniques, eWLB technology greatly reduces manufacturing costs while providing a smaller package footprint with higher Input/Output (I/O) along with increased thermal and electrical performance.
STATS ChipPAC has established a robust, automated eWLB manufacturing process that includes wafer reconstitution, wafer level molding, redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 8” and 12” diameters can be supported, and no bumping is required as the package is essentially built on top of a reconstituted wafer.
“Backed by a strong infrastructure and cost effective manufacturing process, we are able to deliver a high performance solution at a lower cost point with volume and maturity, leveraging the potential of batch panel processing of high density wafer fabrication redistribution technology,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer of STATS ChipPAC.
“We successfully demonstrated the reliability of first generation eWLB technology, ramped to volume production and are positioned to double our production unit volume by the end of 2009.”
Typical applications for eWLB are baseband and RF products for mobile and consumer products. The next generation of eWLB packages enabling reduced cost, multiple routing layers, multiple die, and expansion to larger package size and ball count is now being developed with STATS ChipPAC’s development partners for product offerings starting in 2010.
The eWLB technology provides solutions for semiconductor devices requiring a higher integration level and a greater number of external contacts. Using a combination of traditional ‘front-end’ and ‘back-end’ semiconductor manufacturing techniques, eWLB technology greatly reduces manufacturing costs while providing a smaller package footprint with higher Input/Output (I/O) along with increased thermal and electrical performance.
STATS ChipPAC has established a robust, automated eWLB manufacturing process that includes wafer reconstitution, wafer level molding, redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 8” and 12” diameters can be supported, and no bumping is required as the package is essentially built on top of a reconstituted wafer.
“Backed by a strong infrastructure and cost effective manufacturing process, we are able to deliver a high performance solution at a lower cost point with volume and maturity, leveraging the potential of batch panel processing of high density wafer fabrication redistribution technology,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer of STATS ChipPAC.
“We successfully demonstrated the reliability of first generation eWLB technology, ramped to volume production and are positioned to double our production unit volume by the end of 2009.”
Typical applications for eWLB are baseband and RF products for mobile and consumer products. The next generation of eWLB packages enabling reduced cost, multiple routing layers, multiple die, and expansion to larger package size and ball count is now being developed with STATS ChipPAC’s development partners for product offerings starting in 2010.
Spectre (Communications) joins forces with Avnet
THAME, UK: Avnet Inc. recently entered into a definitive agreement to acquire the assets of the UK-based distributor Spectre (Communications) Ltd.
Spectre is a specialist distributor bringing leading edge communications and wireless solutions to its customers. With immediate effect the former Spectre (Communications) Limited wireless activities will be integrated into the Avnet Memec UK business.
Spectre has established a first class reputation within the RF and wireless market and is offering a wide range of chips, modules, and platforms for Bluetooth, Wi-Fi, GPS, GPRS, VOIP, Zigbee, ULN, WLAN, ISM, and Multimedia Processing. For all of the technologies that Spectre is supporting, they have partnered with global blue chip market leaders.
Patrick Zammit, president of Avnet Electronics Marketing EMEA, commented: “Adding Spectre’s highly skilled technical employees to our UK team will enhance Avnet Memec’s position as the leading pan-European specialist for wireless solutions and will benefit both customers and suppliers alike. The acquisition will also add new RF and Wireless suppliers, such as CSR, SiRF (now part of CSR), CML, Laird and Antenova, to Avnet Memec’s breadth of product offerings in this area and expands and further strengthen Avnet Memec’s presence in the RF and Wireless market.”
Steve Haynes, president Avnet Memec EMEA, added: “The wireless market is a key growth driver within our component industry and the acquisition of Spectre, with their knowledge in Bluetooth, WLAN, GPS, TETRA, ISM and antennas, will strengthen Avnet Memec's market position as the RF and Wireless specialist across Europe.”
The combined organization’s strength in RF & Wireless will be complemented by Avnet’s world-class supply chain management and logistics capabilities.
Spectre is a specialist distributor bringing leading edge communications and wireless solutions to its customers. With immediate effect the former Spectre (Communications) Limited wireless activities will be integrated into the Avnet Memec UK business.
Spectre has established a first class reputation within the RF and wireless market and is offering a wide range of chips, modules, and platforms for Bluetooth, Wi-Fi, GPS, GPRS, VOIP, Zigbee, ULN, WLAN, ISM, and Multimedia Processing. For all of the technologies that Spectre is supporting, they have partnered with global blue chip market leaders.
Patrick Zammit, president of Avnet Electronics Marketing EMEA, commented: “Adding Spectre’s highly skilled technical employees to our UK team will enhance Avnet Memec’s position as the leading pan-European specialist for wireless solutions and will benefit both customers and suppliers alike. The acquisition will also add new RF and Wireless suppliers, such as CSR, SiRF (now part of CSR), CML, Laird and Antenova, to Avnet Memec’s breadth of product offerings in this area and expands and further strengthen Avnet Memec’s presence in the RF and Wireless market.”
Steve Haynes, president Avnet Memec EMEA, added: “The wireless market is a key growth driver within our component industry and the acquisition of Spectre, with their knowledge in Bluetooth, WLAN, GPS, TETRA, ISM and antennas, will strengthen Avnet Memec's market position as the RF and Wireless specialist across Europe.”
The combined organization’s strength in RF & Wireless will be complemented by Avnet’s world-class supply chain management and logistics capabilities.
Tektronix makes with two new additions in DDR test and validation portfolio
BEAVERTON, USA: Tektronix, Inc., a leading worldwide provider of test, measurement and monitoring instrumentation, today announced enhancements and upgrades to its market-leading DDR test and validation portfolio.
New interposers being introduced for the Tektronix TLA7000 Series Logic Analyzers provide engineers with bus capture and analysis for the latest DDR3-1867 standard. The new interposers bring a cost effective test set up to the TLA7000 Series, making memory bus capture accessible to more designers.
Tektronix is also announcing the industry’s first electrical test verification for LP-DDR2 – a new energy efficient version of the popular DDR standard. These new offerings add to the comprehensive, integrated DDR memory solution from Tektronix which provides insight into validating and improving designs of engineers.
DDR3-1867 is the latest generation of double-data-rate memory technology and is now included in the latest release of the DDR3 standard specification from JEDEC, the standards organization for DDR memory. Designed to meet the increasing demand for faster performance in such applications as PC gaming, servers, super-computing, notebooks and high-definition television, DDR3-1867 offers such advantages as a higher data rate and lower power consumption.
The Tektronix TLA7000 series of Logic Analyzers, along with the new interposer solutions from Nexus Technology, Inc. and supporting software give designers a complete set of debug and validation tools for DDR3, including high-speed DDR3-1867. Nexus Technology is the embedded solutions tool partner of Tektronix.
“Memory system validation and debug requires instruments with superior signal capture, measurement accuracy, powerful triggering and high performance probing,” said Dave Farrell, General Manager, Logic Analyzers Product Line, Tektronix, Inc. “By working with Nexus Technology we are able to offer our customers a way to gain easy, cost-effective access to DDR3 signals and deliver support for higher data rates and clock frequencies.”
“By working closely with Tektronix, our DDR3 solutions deliver unrivaled analog and digital validation of DDR3 Memory at affordable price points,” said Robert Shelsky, President, Nexus Technology.
Ultra-High Sampling Resolution
The TLA7000 provides the performance and features engineers require for fast, reliable DDR3 design and validation. For instance, MagniVu ultra-high sampling resolution of 20ps on the TLA7BBx modules allows design engineers to troubleshoot difficult problems as well as verify timing margins across hundreds of channels.
The iCapture Analog Mux on the TLA7BBx modules enables the use of an external oscilloscope to view the analog character of a signal using a single probing configuration for both the logic analyzer and oscilloscope, saving time and minimizing setup complexity – a capability unmatched by any other logic analyzer vendor.
The Nexus memory solutions come with a set of software components to help design engineers quickly and easily setup the logic analyzer to reliably capture DDR3 bus data. The software also provides a decoded view of the DDR bus activity and information about any violations in the DDR bus protocol.
First LP-DDR2 test support
LP-DDR2 is the latest low-power variant of DDR memory technology that offers significant power savings for portable and handheld devices, such as smartphones.
Tektronix is the first test equipment vendor to offer a solution for LP-DDR2 electrical validation and test based on the JEDEC specification JESD209-2A. The new version of Tektronix DDR Memory Bus Analysis software (Option DDRA) for Tektronix real time oscilloscopes such as the DPO7000 Series and the high performance DPO70000 Series now includes support for LP-DDR2.
Tektronix DDR Memory Bus Analysis software enables engineers to automatically identify DDR1, LP-DDR1, DDR2, DDR3, GDDR3 and now LP-DDR2 reads and writes and to clearly see and analyze how analog anomalies are affecting DDR memory. It is the ideal tool for electrical verification of DDR standards.
The new NexusDDR3-1867 Interposers will be available in December 2009.
New interposers being introduced for the Tektronix TLA7000 Series Logic Analyzers provide engineers with bus capture and analysis for the latest DDR3-1867 standard. The new interposers bring a cost effective test set up to the TLA7000 Series, making memory bus capture accessible to more designers.
Tektronix is also announcing the industry’s first electrical test verification for LP-DDR2 – a new energy efficient version of the popular DDR standard. These new offerings add to the comprehensive, integrated DDR memory solution from Tektronix which provides insight into validating and improving designs of engineers.
DDR3-1867 is the latest generation of double-data-rate memory technology and is now included in the latest release of the DDR3 standard specification from JEDEC, the standards organization for DDR memory. Designed to meet the increasing demand for faster performance in such applications as PC gaming, servers, super-computing, notebooks and high-definition television, DDR3-1867 offers such advantages as a higher data rate and lower power consumption.
The Tektronix TLA7000 series of Logic Analyzers, along with the new interposer solutions from Nexus Technology, Inc. and supporting software give designers a complete set of debug and validation tools for DDR3, including high-speed DDR3-1867. Nexus Technology is the embedded solutions tool partner of Tektronix.
“Memory system validation and debug requires instruments with superior signal capture, measurement accuracy, powerful triggering and high performance probing,” said Dave Farrell, General Manager, Logic Analyzers Product Line, Tektronix, Inc. “By working with Nexus Technology we are able to offer our customers a way to gain easy, cost-effective access to DDR3 signals and deliver support for higher data rates and clock frequencies.”
“By working closely with Tektronix, our DDR3 solutions deliver unrivaled analog and digital validation of DDR3 Memory at affordable price points,” said Robert Shelsky, President, Nexus Technology.
Ultra-High Sampling Resolution
The TLA7000 provides the performance and features engineers require for fast, reliable DDR3 design and validation. For instance, MagniVu ultra-high sampling resolution of 20ps on the TLA7BBx modules allows design engineers to troubleshoot difficult problems as well as verify timing margins across hundreds of channels.
The iCapture Analog Mux on the TLA7BBx modules enables the use of an external oscilloscope to view the analog character of a signal using a single probing configuration for both the logic analyzer and oscilloscope, saving time and minimizing setup complexity – a capability unmatched by any other logic analyzer vendor.
The Nexus memory solutions come with a set of software components to help design engineers quickly and easily setup the logic analyzer to reliably capture DDR3 bus data. The software also provides a decoded view of the DDR bus activity and information about any violations in the DDR bus protocol.
First LP-DDR2 test support
LP-DDR2 is the latest low-power variant of DDR memory technology that offers significant power savings for portable and handheld devices, such as smartphones.
Tektronix is the first test equipment vendor to offer a solution for LP-DDR2 electrical validation and test based on the JEDEC specification JESD209-2A. The new version of Tektronix DDR Memory Bus Analysis software (Option DDRA) for Tektronix real time oscilloscopes such as the DPO7000 Series and the high performance DPO70000 Series now includes support for LP-DDR2.
Tektronix DDR Memory Bus Analysis software enables engineers to automatically identify DDR1, LP-DDR1, DDR2, DDR3, GDDR3 and now LP-DDR2 reads and writes and to clearly see and analyze how analog anomalies are affecting DDR memory. It is the ideal tool for electrical verification of DDR standards.
The new NexusDDR3-1867 Interposers will be available in December 2009.
STARC adopts Atrenta SpyGlass-Constraints SDC equivalence verification capability
TOKYO, JAPAN: Atrenta Inc., the leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, announced the integration of the SpyGlass-Constraints SDC equivalence verification capability into the production flow from the Semiconductor Technology Academic Research Center (STARC).
Atrenta’s SpyGlass-Constraints product offers a broad range of features to identify timing constraint issues in SoC designs. Capabilities range from constraint correctness and completeness checking through structural analysis and advanced formal techniques for the verification of timing exceptions.
The SpyGlass-Constraints SDC equivalence capability represents a significant enhancement to Atrenta’s existing timing constraint verification solution. By ensuring that timing constraints remain consistent with the design intent as the design undergoes transformations from RTL through final netlist, implementation iterations are reduced substantially.
SpyGlass-Constraints structural and formal verification capabilities are already incorporated into version 3.5 of the STARCAD-CEL reference flow. STARC engineers conducted an exhaustive evaluation of the new SDC equivalence checking capability on a broad range of test case designs, and were able to show that this technology added even further significant value.
“In our evaluations, we found that the SpyGlass-Constraints SDC equivalence capability allowed us to identify and fix a range of issues typically encountered when a design and its associated timing constraints are not maintained in a consistent manner,” said Nobuyuki Nishiguchi, vice president and general manager at STARC.
“We view constraint verification as a continuous process –- it is essential to be able to verify block level constraints in the context of a chip, and ensure that constraints remain applicable as the design undergoes transformations.”
“Atrenta is constantly enhancing its capabilities for Early Design Closure,” said Mike Gianfagna, vice president of marketing at Atrenta. “STARC’s rigorous qualification process for SpyGlass-Constraints has moved us a step closer to validating our value as a critical tool in chip design flows for accelerating timing closure.”
Atrenta’s SpyGlass-Constraints product offers a broad range of features to identify timing constraint issues in SoC designs. Capabilities range from constraint correctness and completeness checking through structural analysis and advanced formal techniques for the verification of timing exceptions.
The SpyGlass-Constraints SDC equivalence capability represents a significant enhancement to Atrenta’s existing timing constraint verification solution. By ensuring that timing constraints remain consistent with the design intent as the design undergoes transformations from RTL through final netlist, implementation iterations are reduced substantially.
SpyGlass-Constraints structural and formal verification capabilities are already incorporated into version 3.5 of the STARCAD-CEL reference flow. STARC engineers conducted an exhaustive evaluation of the new SDC equivalence checking capability on a broad range of test case designs, and were able to show that this technology added even further significant value.
“In our evaluations, we found that the SpyGlass-Constraints SDC equivalence capability allowed us to identify and fix a range of issues typically encountered when a design and its associated timing constraints are not maintained in a consistent manner,” said Nobuyuki Nishiguchi, vice president and general manager at STARC.
“We view constraint verification as a continuous process –- it is essential to be able to verify block level constraints in the context of a chip, and ensure that constraints remain applicable as the design undergoes transformations.”
“Atrenta is constantly enhancing its capabilities for Early Design Closure,” said Mike Gianfagna, vice president of marketing at Atrenta. “STARC’s rigorous qualification process for SpyGlass-Constraints has moved us a step closer to validating our value as a critical tool in chip design flows for accelerating timing closure.”
Photronics named supplier of the year by TowerJazz
BROOKFIELD, USA: Photronics Inc., a worldwide leader in supplying innovative imaging technology solutions for the global electronics industry, announced that TowerJazz, a global specialty foundry leader has awarded the Company with its Photomask Supplier of the Year Award for outstanding service and support.
TowerJazz utilizes a comprehensive Supplier Rating Program which quantitatively measures Quality, Commercial Performance, Cycle Time, Technology Capability and Customer Support. While taking top honors among photomask suppliers, Photronics achieved perfect scores for both Quality and On-time Delivery performance.
Constantine (“Deno”) Macricostas, Photronics’ Chairman and CEO commented: “We are privileged to receive this award from TowerJazz. For many years, our companies have been working closely together to assist TowerJazz’s success in the competitive global foundry marketplace. This award demonstrates the core values of outstanding customer service, and manufacturing excellence Photronics provides to its customers.”
“Photronics continues to deliver both quality and value for TowerJazz. Exceptional on-time delivery performance has become the norm even on expedited orders. In addition, their on-site Customer Support personnel are integral and valued members of our Operations team. We congratulate Photronics on this award and their proven commitment to our success,” stated Nabil Alali, Senior Vice President of Operations, TowerJazz.
TowerJazz utilizes a comprehensive Supplier Rating Program which quantitatively measures Quality, Commercial Performance, Cycle Time, Technology Capability and Customer Support. While taking top honors among photomask suppliers, Photronics achieved perfect scores for both Quality and On-time Delivery performance.
Constantine (“Deno”) Macricostas, Photronics’ Chairman and CEO commented: “We are privileged to receive this award from TowerJazz. For many years, our companies have been working closely together to assist TowerJazz’s success in the competitive global foundry marketplace. This award demonstrates the core values of outstanding customer service, and manufacturing excellence Photronics provides to its customers.”
“Photronics continues to deliver both quality and value for TowerJazz. Exceptional on-time delivery performance has become the norm even on expedited orders. In addition, their on-site Customer Support personnel are integral and valued members of our Operations team. We congratulate Photronics on this award and their proven commitment to our success,” stated Nabil Alali, Senior Vice President of Operations, TowerJazz.
NI delivers Windows 7 support for engineers and scientists
AUSTIN, USA: National Instruments announced software and hardware compatibility with Windows 7, the latest operating system from Microsoft, to help engineers and scientists attain faster performance and higher throughput within their applications.
Engineers and scientists who are considering upgrading to the latest computer hardware can take advantage of several new features in the new operating system. This release, which includes performance and usability enhancements, provides a smooth upgrade experience and improves the environment for hardware and software compatibility, making it ideal for measurement and workstation applications.
Windows 7 contains features that provide increased USB data acquisition throughput and take full advantage of multicore processors to improve responsiveness and offer compatibility with the latest computer technologies, including support for PCI Express and 64-bit processors.
"Next-generation measurement systems need to have high throughput and fast performance, as engineers and scientists look for new ways to meet constantly increasing demands for speed in their applications," said Jane Boulware, general manager of US Windows Client at Microsoft. "The benchmarks provided by National Instruments with Windows 7 show engineers an effective method for tackling this issue."
Increased USB throughput
By combining Windows 7 with the LabVIEW graphical design platform for test, control and embedded system development, engineers and scientists can achieve efficiency gains including elimination of non-necessary timers, selective hub suspension and lower enumeration time for USB flash devices, which increase the performance of USB test and measurement devices.
In recent benchmarks of the new NI CompactDAQ chassis with LabVIEW, engineers observed a 10 percent increase in overall attainable bandwidth in Windows 7 as compared to the same hardware running on Windows XP. The increased hardware performance combined with the multicore optimization of both the Windows 7 operating system and the LabVIEW development environment result in a performance increase of up to 20 percent when performing high-speed or multifunction I/O measurements.
To take advantage of these performance increases, engineers may need to install new drivers. Drivers compatible with Windows 7 are available for download from National Instruments at www.ni.com/windows7.
Improved multicore use and multitasking capability
Data acquisition applications written in LabVIEW and using NI hardware on a multicore computer will benefit from the improvements in Windows 7 designed to further optimize the use of these processors.
LabVIEW is an inherently multithreaded software platform that assigns independent, asynchronous processes to separate threads that can be executed in parallel by separate computer cores. LabVIEW programmers can create multiple computationally intensive tasks in a single application to run in parallel and optimize the use of all available cores.
Engineers and scientists can use NI drivers such as NI-DAQmx, which are also multithreaded, to efficiently create high-performance acquisition and analysis applications, without having to manually spawn and manage separate threads. A benchmark LabVIEW application with four parallel loops on a quad-core machine executes up to 8 percent faster in Windows 7, compared to Windows XP. Additionally, an NI TestStand parallel sequence benchmark application executes up to 10 percent faster.
"For more than 30 years, NI has continued to deliver on our promise of innovation and continuous improvement in order to give engineers and scientists the tools to be successful, whether you have a simple data acquisition application or a more complex system," said Jon Bellin, vice president of R&D for application and system software at National Instruments.
"Our focus on optimization for multicore systems, including the benchmarks we have provided for multicore systems using Windows 7, is an example of our dedication to creating products that help engineers do more."
Enhanced functionality for PCI Express
Integrating Windows 7 with the PCI Express bus in products such as NI X Series (DAQ) devices more than doubles data throughput compared to using the traditional PCI bus.
PCI Express offers several benefits to data acquisition applications, including dedicated bandwidth to each device of up to 250 MB/s in each direction. With this additional bandwidth, engineers and scientists can acquire larger quantities of analog, digital and counter data; and, due to the dedicated nature of the bus, engineers can expand their systems to include multiple DAQ devices.
Windows 7 provides native support for 64-bit hardware, and measurement applications running on 64-bit hardware and software can take advantage of a larger amount of physical memory than 32-bit systems. Furthermore, when combined with Windows 7 and NI drivers, additional registers on a 64-bit processor can increase application execution speeds up to 10 percent.
Engineers and scientists who are considering upgrading to the latest computer hardware can take advantage of several new features in the new operating system. This release, which includes performance and usability enhancements, provides a smooth upgrade experience and improves the environment for hardware and software compatibility, making it ideal for measurement and workstation applications.
Windows 7 contains features that provide increased USB data acquisition throughput and take full advantage of multicore processors to improve responsiveness and offer compatibility with the latest computer technologies, including support for PCI Express and 64-bit processors.
"Next-generation measurement systems need to have high throughput and fast performance, as engineers and scientists look for new ways to meet constantly increasing demands for speed in their applications," said Jane Boulware, general manager of US Windows Client at Microsoft. "The benchmarks provided by National Instruments with Windows 7 show engineers an effective method for tackling this issue."
Increased USB throughput
By combining Windows 7 with the LabVIEW graphical design platform for test, control and embedded system development, engineers and scientists can achieve efficiency gains including elimination of non-necessary timers, selective hub suspension and lower enumeration time for USB flash devices, which increase the performance of USB test and measurement devices.
In recent benchmarks of the new NI CompactDAQ chassis with LabVIEW, engineers observed a 10 percent increase in overall attainable bandwidth in Windows 7 as compared to the same hardware running on Windows XP. The increased hardware performance combined with the multicore optimization of both the Windows 7 operating system and the LabVIEW development environment result in a performance increase of up to 20 percent when performing high-speed or multifunction I/O measurements.
To take advantage of these performance increases, engineers may need to install new drivers. Drivers compatible with Windows 7 are available for download from National Instruments at www.ni.com/windows7.
Improved multicore use and multitasking capability
Data acquisition applications written in LabVIEW and using NI hardware on a multicore computer will benefit from the improvements in Windows 7 designed to further optimize the use of these processors.
LabVIEW is an inherently multithreaded software platform that assigns independent, asynchronous processes to separate threads that can be executed in parallel by separate computer cores. LabVIEW programmers can create multiple computationally intensive tasks in a single application to run in parallel and optimize the use of all available cores.
Engineers and scientists can use NI drivers such as NI-DAQmx, which are also multithreaded, to efficiently create high-performance acquisition and analysis applications, without having to manually spawn and manage separate threads. A benchmark LabVIEW application with four parallel loops on a quad-core machine executes up to 8 percent faster in Windows 7, compared to Windows XP. Additionally, an NI TestStand parallel sequence benchmark application executes up to 10 percent faster.
"For more than 30 years, NI has continued to deliver on our promise of innovation and continuous improvement in order to give engineers and scientists the tools to be successful, whether you have a simple data acquisition application or a more complex system," said Jon Bellin, vice president of R&D for application and system software at National Instruments.
"Our focus on optimization for multicore systems, including the benchmarks we have provided for multicore systems using Windows 7, is an example of our dedication to creating products that help engineers do more."
Enhanced functionality for PCI Express
Integrating Windows 7 with the PCI Express bus in products such as NI X Series (DAQ) devices more than doubles data throughput compared to using the traditional PCI bus.
PCI Express offers several benefits to data acquisition applications, including dedicated bandwidth to each device of up to 250 MB/s in each direction. With this additional bandwidth, engineers and scientists can acquire larger quantities of analog, digital and counter data; and, due to the dedicated nature of the bus, engineers can expand their systems to include multiple DAQ devices.
Windows 7 provides native support for 64-bit hardware, and measurement applications running on 64-bit hardware and software can take advantage of a larger amount of physical memory than 32-bit systems. Furthermore, when combined with Windows 7 and NI drivers, additional registers on a 64-bit processor can increase application execution speeds up to 10 percent.
GSI Technology intros revolutionary next generation SRAM architecture
SANTA CLARA, USA: GSI Technology announced the availability of SigmaQuad-IIIe and SigmaDDR-IIIe, two new SRAM products whose revolutionary architecture provides the ultimate in system performance, reliability, and flexibility for applications that require a high random address rate.
They are specifically designed to meet the growing memory requirements of networking systems -— the backbone of the Internet.
"To most of the world, 'fast memory' means high bandwidth data, while in SRAM circles it has typically meant low latency," said David Chapman, Vice President of Marketing and Applications Engineering for GSI. "But today, networking system designers need something more. The IIIe family delivers more, including the first memory product ever that can sustain continuous fully random read and write transactions every single nanosecond.
"This sort of capability is terribly important to those wishing to measurably enhance the performance of networking systems," noted Chapman.
"And because these parts allow designers to solve problems directly rather than through increasing architectural complexity, these SRAMs help cut development costs and improve our customer’s time-to-market. Although improvement in random address rate — the measure of how often a new fully random access can be executed in a memory device — is sure to be seen as the biggest contribution of this product family, the series also includes the highest bandwidth SRAMs available on the open market and the most complete set of signal integrity improvement tools SRAM users have ever had."
At 625 MHz, the new 72Mbit Type–IIIe products feature the market’s fastest available Burst of 4 operation, which is 14 percent faster than the nearest competitor, and the market's fastest Burst of 2 operation, which is 50 percent faster than the nearest competitor.
Packaged in a 260 BGA with checkerboard power and ground pin out, these devices deliver both high transaction rate operations and very high data bandwidth with dramatically improved signal integrity to control system noise. Additionally, new features have been added to ease host memory controller design and reduce Soft Error Rate (SER).
GSI’s SigmaQuad/SigmaDDR-IIIe devices offer both obvious and subtle improvements over previous generations of Quad and DDR SRAM products. An improved input clocking scheme provides the ability to optimize input setup and hold times in a variety of board layout schemes and an improved output clocking scheme provides a more consistent and therefore a wider data output valid window.
In addition, user-configurable output echo clocks can be centered or edge-aligned. There is also a selectable read pipeline length to maximize input clock frequency. Another feature is highly robust input termination available on all synchronous inputs to minimize signal reflections.
GSI Technology's 72Mbit SigmaQuad/SigmaDDR-IIIe products are sampling now.
They are specifically designed to meet the growing memory requirements of networking systems -— the backbone of the Internet.
"To most of the world, 'fast memory' means high bandwidth data, while in SRAM circles it has typically meant low latency," said David Chapman, Vice President of Marketing and Applications Engineering for GSI. "But today, networking system designers need something more. The IIIe family delivers more, including the first memory product ever that can sustain continuous fully random read and write transactions every single nanosecond.
"This sort of capability is terribly important to those wishing to measurably enhance the performance of networking systems," noted Chapman.
"And because these parts allow designers to solve problems directly rather than through increasing architectural complexity, these SRAMs help cut development costs and improve our customer’s time-to-market. Although improvement in random address rate — the measure of how often a new fully random access can be executed in a memory device — is sure to be seen as the biggest contribution of this product family, the series also includes the highest bandwidth SRAMs available on the open market and the most complete set of signal integrity improvement tools SRAM users have ever had."
At 625 MHz, the new 72Mbit Type–IIIe products feature the market’s fastest available Burst of 4 operation, which is 14 percent faster than the nearest competitor, and the market's fastest Burst of 2 operation, which is 50 percent faster than the nearest competitor.
Packaged in a 260 BGA with checkerboard power and ground pin out, these devices deliver both high transaction rate operations and very high data bandwidth with dramatically improved signal integrity to control system noise. Additionally, new features have been added to ease host memory controller design and reduce Soft Error Rate (SER).
GSI’s SigmaQuad/SigmaDDR-IIIe devices offer both obvious and subtle improvements over previous generations of Quad and DDR SRAM products. An improved input clocking scheme provides the ability to optimize input setup and hold times in a variety of board layout schemes and an improved output clocking scheme provides a more consistent and therefore a wider data output valid window.
In addition, user-configurable output echo clocks can be centered or edge-aligned. There is also a selectable read pipeline length to maximize input clock frequency. Another feature is highly robust input termination available on all synchronous inputs to minimize signal reflections.
GSI Technology's 72Mbit SigmaQuad/SigmaDDR-IIIe products are sampling now.
Fujitsu develops world's first technology for low-temperature full-surface direct formation of graphene transistors on large-scale substrates
KAWASAKI, JAPAN: Fujitsu Laboratories Ltd. recently announced, as a world first, the development of a novel technology for forming graphene transistors directly on the entire surface of large-scale insulating substrates at low temperatures while employing chemical-vapor deposition (CVD) techniques which are in widespread use in semiconductor manufacturing.
Compared to the temperatures of 800-1000°C at which graphene is formed with conventional methods, Fujitsu has succeeded in significantly lowering the graphene fabrication-temperature to 650°C, thus allowing for graphene transistors to be formed directly on a variety of insulator substrates, including substrates that are sensitive to the higher temperatures.
Graphene is a nano-scale carbon material (nano-carbon) with the potential to be the material used in next-generation low-voltage, low-power transistors, as graphene features high-electron and hole mobility characteristics.
Details of this technology will be presented at the Materials Research Society 2009 (MRS 2009) Fall Meeting, to be held from November 30 to December 4 in Boston.
Background
Currently, silicon is the material used for transistor channels - the conduits that pass electricity - in LSIs, and through miniaturization of devices, higher speeds and lower power consumption have been realized. However, in recent years, miniaturization technology has been approaching its limits, and achieving further higher performance is becoming increasingly more difficult.
This issue has led to a wave of active development of next-generation transistors using materials such as germanium, gallium arsenide, or graphene as channel materials.
Graphene is essentially a single layer of the multi-layered graphite that is used, for example, as pencil lead. The individual carbon atoms in graphene are linked into a hexagonal lattice that is laid out in a flat sheet.
Single sheets of graphene were first separated successfully in 2004, and were found to feature excellent electrical characteristics. Experiments showed that graphene has extremely high electron mobility compared to silicon that is typically used in semiconductors, and it is anticipated that graphene could be used to produce fast, low-voltage transistors.
Technological challenges
Prototype transistors using graphene have been produced since several years ago. Laying the graphene on the substrate involved one of the following procedures:
1. Peel-off/transfer method
A method in which a layer is peeled off from a graphite crystal using tape, and transferred to the substrate.
2. CVD/transfer method
A method in which graphene is formed on a film of metallic catalyst at temperatures of approximately 800-1000°C, and then transferred to a different substrate.
3. Silicon-carbide (SiC) surface decomposition method
A method in which a substrate of SiC, a semiconductor, is heat-treated at 1200-1500°C to form graphene on the SiC surface.
The CVD/transfer method using a metallic catalyst has the advantage that graphene can be formed on any kind of substrate, but because it is impossible to form transistors on conductive metal, the graphene that had been formed on one substrate would be transferred to an insulating substrate to make the transistors.
The CVD/transferring method is prone to forming wrinkles in the thin-film graphene, and is not readily amenable to use with the 300-mm wafer size that is common today. Practical implementation of the CVD/transferring method would require the ability to produce transistors that are consistent regardless of substrate size.
An additional issue is that as graphene transistors are usually formed at temperatures of 800°C or higher, there was a limit to the types of substrates that graphene could be used with.
Overview of Fujitsu's technology
As a world first, Fujitsu Laboratories developed novel technology that allows for graphene to be formed on insulating film substrate via CVD at the low fabrication-temperature of 650°C, enabling graphene-based transistors to be directly formed on the entire surface of substrates.
Although the test substrate employed was a 75-mm silicon substrate (wafer) with oxide film, the new technique is applicable to larger 300-mm wafers as well.
Compared to the temperatures of 800-1000°C at which graphene is formed with conventional methods, Fujitsu has succeeded in significantly lowering the graphene fabrication-temperature to 650°C, thus allowing for graphene transistors to be formed directly on a variety of insulator substrates, including substrates that are sensitive to the higher temperatures.
Graphene is a nano-scale carbon material (nano-carbon) with the potential to be the material used in next-generation low-voltage, low-power transistors, as graphene features high-electron and hole mobility characteristics.
Details of this technology will be presented at the Materials Research Society 2009 (MRS 2009) Fall Meeting, to be held from November 30 to December 4 in Boston.
Background
Currently, silicon is the material used for transistor channels - the conduits that pass electricity - in LSIs, and through miniaturization of devices, higher speeds and lower power consumption have been realized. However, in recent years, miniaturization technology has been approaching its limits, and achieving further higher performance is becoming increasingly more difficult.
This issue has led to a wave of active development of next-generation transistors using materials such as germanium, gallium arsenide, or graphene as channel materials.
Graphene is essentially a single layer of the multi-layered graphite that is used, for example, as pencil lead. The individual carbon atoms in graphene are linked into a hexagonal lattice that is laid out in a flat sheet.
Single sheets of graphene were first separated successfully in 2004, and were found to feature excellent electrical characteristics. Experiments showed that graphene has extremely high electron mobility compared to silicon that is typically used in semiconductors, and it is anticipated that graphene could be used to produce fast, low-voltage transistors.
Technological challenges
Prototype transistors using graphene have been produced since several years ago. Laying the graphene on the substrate involved one of the following procedures:
1. Peel-off/transfer method
A method in which a layer is peeled off from a graphite crystal using tape, and transferred to the substrate.
2. CVD/transfer method
A method in which graphene is formed on a film of metallic catalyst at temperatures of approximately 800-1000°C, and then transferred to a different substrate.
3. Silicon-carbide (SiC) surface decomposition method
A method in which a substrate of SiC, a semiconductor, is heat-treated at 1200-1500°C to form graphene on the SiC surface.
The CVD/transfer method using a metallic catalyst has the advantage that graphene can be formed on any kind of substrate, but because it is impossible to form transistors on conductive metal, the graphene that had been formed on one substrate would be transferred to an insulating substrate to make the transistors.
The CVD/transferring method is prone to forming wrinkles in the thin-film graphene, and is not readily amenable to use with the 300-mm wafer size that is common today. Practical implementation of the CVD/transferring method would require the ability to produce transistors that are consistent regardless of substrate size.
An additional issue is that as graphene transistors are usually formed at temperatures of 800°C or higher, there was a limit to the types of substrates that graphene could be used with.
Overview of Fujitsu's technology
As a world first, Fujitsu Laboratories developed novel technology that allows for graphene to be formed on insulating film substrate via CVD at the low fabrication-temperature of 650°C, enabling graphene-based transistors to be directly formed on the entire surface of substrates.
Although the test substrate employed was a 75-mm silicon substrate (wafer) with oxide film, the new technique is applicable to larger 300-mm wafers as well.
Actel extends Core8051s processor support to RTAX, Axcelerator and IGLOO families
MOUNTAIN VIEW, USA: Continuing to deliver solutions for embedded designers, Actel Corp. today announced that it has extended Core8051s support for its line of high-reliability Axcelerator , radiation-tolerant RTAX and low-power IGLOO FPGAs.
By broadening Core8051s support, Actel enables designers developing high reliability, space-flight or portable embedded designs to take advantage of the strong ecosystem and deep code base that exists for 8051-based processors while simultaneously leveraging the flexibility advantages delivered by Actel FPGAs.
Core8051s is an ASM51-compatible 8-bit microcontroller core that runs programs written for the industry standard 8051. The external SFR interface normally present on 8051 microcontrollers is replaced in Core8051s by an advanced peripheral bus (APB) v3.0 interface.
Designers can use Core8051 to instantiate the main 8051 core logic in Actel FPGA fabric, and via the APB v3.0 bus interface they can easily connect any APB IP peripherals. In addition, designers can now customize their design with only the peripheral functions (timers, UARTs, I/O ports) required for their application, optimizing area and freeing FPGA fabric for additional custom digital circuitry.
With the introduction of this 8-bit microprocessor, Actel expands the range of microprocessor options for designers in several different application areas. For designers of low-power systems, the 8051s offers a low-cost, low-power complement to the ARM Cortex(TM)-M1 32-bit microprocessor.
For designers of space-flight systems and other high-reliability applications, the 8051s adds a small footprint complement to the successful and popular LEON3-FT 32-bit processor, which currently is acquiring space-flight heritage in Actel RTAX2000S FPGAs. Core8051s is already seeing deployment in designs targeting RTAX-S space-flight FPGAs.
Key features:
* High-performance 8-bit microcontroller
* 1 clock per instruction
* ASM51 (8051, 8031, 80C51) compatible
* Can be used with existing 8051 tools and code
* APB bus peripheral interface
* Optional MUL, DIV, DA instructions; can be removed if not used to further reduce core size
* Optional OCI debug block
* Core8051s continues to support low-power ProASIC®3 and Actel Fusion® mixed-signal FPGA families.
Core8051s is available free of charge with Actel's Libero Integrated Design Environment (IDE), using Actel's SmartDesign IP design canvas tool. Libero IDE can be downloaded and installed directly from Actel's website.
The Actel Libero IDE Gold edition is available for Windows XP or Vista free of charge. The Actel Libero IDE Platinum edition is available for Windows and Linux platforms for $2,495. All editions are one-year renewable licenses.
By broadening Core8051s support, Actel enables designers developing high reliability, space-flight or portable embedded designs to take advantage of the strong ecosystem and deep code base that exists for 8051-based processors while simultaneously leveraging the flexibility advantages delivered by Actel FPGAs.
Core8051s is an ASM51-compatible 8-bit microcontroller core that runs programs written for the industry standard 8051. The external SFR interface normally present on 8051 microcontrollers is replaced in Core8051s by an advanced peripheral bus (APB) v3.0 interface.
Designers can use Core8051 to instantiate the main 8051 core logic in Actel FPGA fabric, and via the APB v3.0 bus interface they can easily connect any APB IP peripherals. In addition, designers can now customize their design with only the peripheral functions (timers, UARTs, I/O ports) required for their application, optimizing area and freeing FPGA fabric for additional custom digital circuitry.
With the introduction of this 8-bit microprocessor, Actel expands the range of microprocessor options for designers in several different application areas. For designers of low-power systems, the 8051s offers a low-cost, low-power complement to the ARM Cortex(TM)-M1 32-bit microprocessor.
For designers of space-flight systems and other high-reliability applications, the 8051s adds a small footprint complement to the successful and popular LEON3-FT 32-bit processor, which currently is acquiring space-flight heritage in Actel RTAX2000S FPGAs. Core8051s is already seeing deployment in designs targeting RTAX-S space-flight FPGAs.
Key features:
* High-performance 8-bit microcontroller
* 1 clock per instruction
* ASM51 (8051, 8031, 80C51) compatible
* Can be used with existing 8051 tools and code
* APB bus peripheral interface
* Optional MUL, DIV, DA instructions; can be removed if not used to further reduce core size
* Optional OCI debug block
* Core8051s continues to support low-power ProASIC®3 and Actel Fusion® mixed-signal FPGA families.
Core8051s is available free of charge with Actel's Libero Integrated Design Environment (IDE), using Actel's SmartDesign IP design canvas tool. Libero IDE can be downloaded and installed directly from Actel's website.
The Actel Libero IDE Gold edition is available for Windows XP or Vista free of charge. The Actel Libero IDE Platinum edition is available for Windows and Linux platforms for $2,495. All editions are one-year renewable licenses.
TI intros lowest power 250-MSPS 14-bit ADC
DALLAS, USA: Texas Instruments Inc. (TI) today introduced the first in a new class of high-speed analog-to-digital converters (ADCs) delivering ultra-low power consumption and excellent dynamic performance across wide signal bandwidths from DC up to 550 MHz.
At the maximum sample rate of 250 mega samples per second (MSPS), the 14-bit ADS4149 consumes 30 percent less power, while delivering 3-dB greater signal-to-noise ratio (SNR) than the nearest low-power ADC. This combination of power and performance enables greater efficiency and density while enhancing range and sensitivity in defense, test and measurement, and communications applications.
"Designers of wide-bandwidth applications are challenged to deliver smaller, more portable systems with increased efficiency, while still meeting the highest performance specifications," said Art George, senior vice president of TI's High-Performance Analog business unit.
"This new class of ADCs sets low power benchmarks and allows designers to create denser and more compact systems that extend battery life in radios and test equipment."
Key features and benefits of ADS4149
* ADS4149 consumes as little as 275 mW per channel at 250 MSPS, while offering 72.5-dB SNR at 100-MHz input frequency. Dynamic power scaling reduces power consumption to 215 mW at 160 MSPS.
* Optional buffered analog input provides constant input impedance across time and frequency and eliminates sample-and-hold kickback, simplifying input matching for passive and active analog front ends, while reducing pass band ripple.
* A 1- to 6-dB programmable gain option gives customers flexibility to trade off between SNR and spurious free dynamic range (SFDR) with lowered input voltage swing.
* ADS4149 family includes pin-compatible 12- and 14-bit options at 160 and 250 MSPS and buffered devices to enable customers to easily move to lower resolutions and samples rates without altering their core design.
* Migration path from the ADS6149 allows customers to shift to lower power options.
* TI's TSW1200 digital capture tool facilitates rapid analysis of the ADS4149 evaluation module (EVM). Available high-speed mezzanine connector (HSMC) and FPGA mezzanine connector (FMC) allow ADS4149 EVMs to mate to FPGA EVMs for system-level prototyping to speed development time.
Customers can further speed time-to-market with a complete signal chain for software defined radio and test equipment: dual, 16-bit, 1-GSPS digital-to-analog converter (DAC) (DAC5682Z); wideband, fully differential amplifier (THS4509); programmable digital up and down converter (GC5016); digital pre-distortion solution with crest factor reduction (GC5325); direct quadrature modulator (TRF3703); frequency synthesizer (TRF3761); low-jitter clock generator and synchronizer (CDCE62005, CDCE72010); and high-performance digital signal processors (DSP) (TMS320C6472).
The ADS4149 and companion single configuration parts are available today in a 48-pin QFN package. The ADS4149 is priced at $89 in 1,000-unit quantities. Multi-channel options will be available in 1H2010.
At the maximum sample rate of 250 mega samples per second (MSPS), the 14-bit ADS4149 consumes 30 percent less power, while delivering 3-dB greater signal-to-noise ratio (SNR) than the nearest low-power ADC. This combination of power and performance enables greater efficiency and density while enhancing range and sensitivity in defense, test and measurement, and communications applications.
"Designers of wide-bandwidth applications are challenged to deliver smaller, more portable systems with increased efficiency, while still meeting the highest performance specifications," said Art George, senior vice president of TI's High-Performance Analog business unit.
"This new class of ADCs sets low power benchmarks and allows designers to create denser and more compact systems that extend battery life in radios and test equipment."
Key features and benefits of ADS4149
* ADS4149 consumes as little as 275 mW per channel at 250 MSPS, while offering 72.5-dB SNR at 100-MHz input frequency. Dynamic power scaling reduces power consumption to 215 mW at 160 MSPS.
* Optional buffered analog input provides constant input impedance across time and frequency and eliminates sample-and-hold kickback, simplifying input matching for passive and active analog front ends, while reducing pass band ripple.
* A 1- to 6-dB programmable gain option gives customers flexibility to trade off between SNR and spurious free dynamic range (SFDR) with lowered input voltage swing.
* ADS4149 family includes pin-compatible 12- and 14-bit options at 160 and 250 MSPS and buffered devices to enable customers to easily move to lower resolutions and samples rates without altering their core design.
* Migration path from the ADS6149 allows customers to shift to lower power options.
* TI's TSW1200 digital capture tool facilitates rapid analysis of the ADS4149 evaluation module (EVM). Available high-speed mezzanine connector (HSMC) and FPGA mezzanine connector (FMC) allow ADS4149 EVMs to mate to FPGA EVMs for system-level prototyping to speed development time.
Customers can further speed time-to-market with a complete signal chain for software defined radio and test equipment: dual, 16-bit, 1-GSPS digital-to-analog converter (DAC) (DAC5682Z); wideband, fully differential amplifier (THS4509); programmable digital up and down converter (GC5016); digital pre-distortion solution with crest factor reduction (GC5325); direct quadrature modulator (TRF3703); frequency synthesizer (TRF3761); low-jitter clock generator and synchronizer (CDCE62005, CDCE72010); and high-performance digital signal processors (DSP) (TMS320C6472).
The ADS4149 and companion single configuration parts are available today in a 48-pin QFN package. The ADS4149 is priced at $89 in 1,000-unit quantities. Multi-channel options will be available in 1H2010.
Virage Logic announces Sonic Focus Adaptive Volume for PCs, DTVs, game consoles and telephony products
FREMONT, USA: Virage Logic Corp., the semiconductor industry's trusted IP partner, today announced the availability of its new Sonic Focus Adaptive Volume audio volume normalizing software.
Adaptive Volume normalizes audio levels of movies and music to reduce the need for frequent volume adjustments by the consumer and thereby enhances audio performance in consumer electronics. It has already been licensed for use in PCs, Phone Applications and USB peripherals.
Unlike other normalization techniques, Virage Logic’s Sonic Focus Adaptive Volume employs a predictive algorithm based on human perception of loudness. Adaptive Volume seamlessly adjusts the audio level when switching among DTV programs, movies, music and voice, both reducing uncomfortable loudness and boosting soft audio content.
For example, Adaptive Volume detects and corrects any volume fluctuation between a digital television (DTV) program and a commercial advertisement. Adaptive Volume also adjusts PC audio when a user transitions from a VoIP call to watching internet based content, a DVD or Blu-ray movie or listening to music.
Consumer electronics manufacturers can implement Adaptive Volume with the full range of Virage Logic’s Sonic Focus audio enrichment products to shorten time-to-market and time-to-volume of products that give consumers unsurpassed audio enjoyment. Original Equipment Manufacturers (OEMs) can also benefit from using the Sonic Focus product mastering tools and audio enrichment IP provided by Virage Logic.
These unique tools allow companies to customize audio quality and the magnitude of the volume normalizing effect, thus optimizing the whole audio chain, including audio transducers, speaker cavity and industrial design. This entire tool set provides companies with the ability to produce the very best audio quality and consumer experience in end products such as DTV and PCs.
“Consumers have been challenged by volume level changes for some time, especially with devices that access content on the internet. We see a clear need in the market for a solution that not only smoothes out audio volume levels, regardless of the source of the materials, but also does not crush the audio dynamics inherent in the content,” said Michael Franzi, vice president and general manager of Virage Logic’s Sonic Focus Group.
“Consumer electronics device manufacturers will now be able to easily integrate Adaptive Volume audio IP into multimedia products such as all-in-one PCs, laptops, DTVs, mobile devices and game consoles to differentiate their products and provide consumers a more pleasant and natural listening experience.”
Adaptive Volume normalizes audio levels of movies and music to reduce the need for frequent volume adjustments by the consumer and thereby enhances audio performance in consumer electronics. It has already been licensed for use in PCs, Phone Applications and USB peripherals.
Unlike other normalization techniques, Virage Logic’s Sonic Focus Adaptive Volume employs a predictive algorithm based on human perception of loudness. Adaptive Volume seamlessly adjusts the audio level when switching among DTV programs, movies, music and voice, both reducing uncomfortable loudness and boosting soft audio content.
For example, Adaptive Volume detects and corrects any volume fluctuation between a digital television (DTV) program and a commercial advertisement. Adaptive Volume also adjusts PC audio when a user transitions from a VoIP call to watching internet based content, a DVD or Blu-ray movie or listening to music.
Consumer electronics manufacturers can implement Adaptive Volume with the full range of Virage Logic’s Sonic Focus audio enrichment products to shorten time-to-market and time-to-volume of products that give consumers unsurpassed audio enjoyment. Original Equipment Manufacturers (OEMs) can also benefit from using the Sonic Focus product mastering tools and audio enrichment IP provided by Virage Logic.
These unique tools allow companies to customize audio quality and the magnitude of the volume normalizing effect, thus optimizing the whole audio chain, including audio transducers, speaker cavity and industrial design. This entire tool set provides companies with the ability to produce the very best audio quality and consumer experience in end products such as DTV and PCs.
“Consumers have been challenged by volume level changes for some time, especially with devices that access content on the internet. We see a clear need in the market for a solution that not only smoothes out audio volume levels, regardless of the source of the materials, but also does not crush the audio dynamics inherent in the content,” said Michael Franzi, vice president and general manager of Virage Logic’s Sonic Focus Group.
“Consumer electronics device manufacturers will now be able to easily integrate Adaptive Volume audio IP into multimedia products such as all-in-one PCs, laptops, DTVs, mobile devices and game consoles to differentiate their products and provide consumers a more pleasant and natural listening experience.”
AWR, AMPSA bring multimatch amplifier design technology to Microwave office
EL SEGUNDO, USA & CENTURION, SOUTH AFRICA: AWR, the innovation leader in high-frequency electronic design automation (EDA), and AMPSA, supplier of RF and microwave amplifier design software, today announced a relationship that enables AWR to incorporate AMPSA’s Multimatch amplifier design technology as an optional module into its industry-leading Microwave Office® high-frequency design software.
By making the Multimatch Amplifier Design Wizard (Multimatch ADW) readily available to Microwave Office software users, designers gain ready access to design technology for realizing state-of-the-art, high dynamic range RF and microwave amplifiers (class A and class B).
“The power of Multimatch software comes from its specialized structure and powerful real-world synthesis, analysis, optimization, and artwork capabilities,” said Pieter Abrie, founder of AMPSA. “Incorporating Multimatch as a pre-processor to AWR’s RF and microwave circuit simulator offers a complete, robust, and comprehensive design environment for amplifier designers.”
“The inclusion of the Multimatch ADW in the AWR product portfolio mix streamlines the design flow and improves the efficiency of the user,” said Sherry Hess, vice president of marketing at AWR. ”This partnership continues our ongoing strategy of providing best-in-class tools and technologies that improve the overall design experience of our customers and help them get their products to market quickly.”
By making the Multimatch Amplifier Design Wizard (Multimatch ADW) readily available to Microwave Office software users, designers gain ready access to design technology for realizing state-of-the-art, high dynamic range RF and microwave amplifiers (class A and class B).
“The power of Multimatch software comes from its specialized structure and powerful real-world synthesis, analysis, optimization, and artwork capabilities,” said Pieter Abrie, founder of AMPSA. “Incorporating Multimatch as a pre-processor to AWR’s RF and microwave circuit simulator offers a complete, robust, and comprehensive design environment for amplifier designers.”
“The inclusion of the Multimatch ADW in the AWR product portfolio mix streamlines the design flow and improves the efficiency of the user,” said Sherry Hess, vice president of marketing at AWR. ”This partnership continues our ongoing strategy of providing best-in-class tools and technologies that improve the overall design experience of our customers and help them get their products to market quickly.”
Consumers demand better access to multimedia content on portable devices, but at zero device cost premium
SUNNYVALE, USA & FLEET, ENGLAND: Users of mobile computing and portable communications devices want to access more multimedia content, but are being held back by the lack of availability of low-cost, converged functionality devices, according to the results of a survey conducted by ABI Research on behalf of Mirics Semiconductor.
The survey results also highlight that while users of portable consumer electronics (CE) devices have a clear vision of the increased functionality they would like from their device, they are not prepared to pay a price premium for these added features.
The research, which was recently conducted among 1000 adults in the USA, UK and Japan who regularly use a mobile CE device, such as a notebook computer or smart phone, revealed consumer interest in a wide variety of services that all rely on differing wireless communication technologies.
Global Positioning System (GPS) location-based services, Wi-Fi Internet connection and the ability to receive live TV content were among the most frequent functional requests in consumers’ future devices, as was the ability to easily transfer large files wirelessly. Unsurprisingly, faster Internet access was the most popular choice.
Consumers in all regions expressed general satisfaction with the physical aspects of their existing primary device: overall size, weight and screen size were judged ‘just right’ by the majority. The implication is that manufacturers are catering successfully to the needs of most users in this area.
Two thirds of those surveyed already have a Wi-Fi enabled mobile device, and the majority of the remainder expressed interest in using it in a future device. More than 50% of the respondents would like to use their mobile device as an ‘electronic wallet’ to pay for, for example, retail goods and public transport services. A mobile device equipped with NFC (Near Field Communication) wireless technology would support such functionality.
Over 40 percent of respondents are accessing more content than a year ago. The most commonly cited reason for this is that their current device has the features that enable easier access to multimedia content. In addition, 43 percent of the sample had accessed live TV or video on demand (VoD) on their mobile device.
Looking forward, 82 percent of respondents predicted they would be accessing more or at least the same content on their mobile devices in one year’s time compared to their current usage. When asked what type of mobile content they would like that they cannot or do not access now, the most popular request was to receive live TV, followed by VoD.
Those interested in receiving live TV indicated they would be prepared to pay on average $5-8 per month for the service. However, when asked how much extra they would be prepared to pay for a new primary mobile device assuming it had all the features and functionality they wanted, the most common response – given by 40 percent of those surveyed – was nothing, and only 16 percent of all respondents were prepared to pay up to $25 for this functionality.
Kevin Burden, Mobile Device Director, ABI Research, commented: "This survey has shown that consumers on the whole are happy with the form factor of their mobile devices, and are now most interested in the available functional capabilities of these devices.
"Strikingly, the survey suggests that whilst consumers are willing to pay a modest premium to access a particular service, the majority are not prepared to pay an appreciable amount in terms of higher device cost for this additional functionality. This reveals the pressure on portable CE device manufacturers to deliver converged functionality without raising costs.”
Chet Babla, Marcom Director, Mirics Semiconductor, added: “Wi-Fi, GPS, streamed audio and video content, NFC and live TV all require different wireless technologies to be supported in portable devices to deliver the multimedia experience that consumers want. The challenge for device developers is to support these multiple wireless technologies without significantly impacting end-product price.
"Innovative approaches such as software-based modems - whereby key wireless functional blocks conventionally implemented in silicon hardware are replaced with the flexibility of software - will be crucial to achieving this convergence at an acceptable cost point.”
The survey results also highlight that while users of portable consumer electronics (CE) devices have a clear vision of the increased functionality they would like from their device, they are not prepared to pay a price premium for these added features.
The research, which was recently conducted among 1000 adults in the USA, UK and Japan who regularly use a mobile CE device, such as a notebook computer or smart phone, revealed consumer interest in a wide variety of services that all rely on differing wireless communication technologies.
Global Positioning System (GPS) location-based services, Wi-Fi Internet connection and the ability to receive live TV content were among the most frequent functional requests in consumers’ future devices, as was the ability to easily transfer large files wirelessly. Unsurprisingly, faster Internet access was the most popular choice.
Consumers in all regions expressed general satisfaction with the physical aspects of their existing primary device: overall size, weight and screen size were judged ‘just right’ by the majority. The implication is that manufacturers are catering successfully to the needs of most users in this area.
Two thirds of those surveyed already have a Wi-Fi enabled mobile device, and the majority of the remainder expressed interest in using it in a future device. More than 50% of the respondents would like to use their mobile device as an ‘electronic wallet’ to pay for, for example, retail goods and public transport services. A mobile device equipped with NFC (Near Field Communication) wireless technology would support such functionality.
Over 40 percent of respondents are accessing more content than a year ago. The most commonly cited reason for this is that their current device has the features that enable easier access to multimedia content. In addition, 43 percent of the sample had accessed live TV or video on demand (VoD) on their mobile device.
Looking forward, 82 percent of respondents predicted they would be accessing more or at least the same content on their mobile devices in one year’s time compared to their current usage. When asked what type of mobile content they would like that they cannot or do not access now, the most popular request was to receive live TV, followed by VoD.
Those interested in receiving live TV indicated they would be prepared to pay on average $5-8 per month for the service. However, when asked how much extra they would be prepared to pay for a new primary mobile device assuming it had all the features and functionality they wanted, the most common response – given by 40 percent of those surveyed – was nothing, and only 16 percent of all respondents were prepared to pay up to $25 for this functionality.
Kevin Burden, Mobile Device Director, ABI Research, commented: "This survey has shown that consumers on the whole are happy with the form factor of their mobile devices, and are now most interested in the available functional capabilities of these devices.
"Strikingly, the survey suggests that whilst consumers are willing to pay a modest premium to access a particular service, the majority are not prepared to pay an appreciable amount in terms of higher device cost for this additional functionality. This reveals the pressure on portable CE device manufacturers to deliver converged functionality without raising costs.”
Chet Babla, Marcom Director, Mirics Semiconductor, added: “Wi-Fi, GPS, streamed audio and video content, NFC and live TV all require different wireless technologies to be supported in portable devices to deliver the multimedia experience that consumers want. The challenge for device developers is to support these multiple wireless technologies without significantly impacting end-product price.
"Innovative approaches such as software-based modems - whereby key wireless functional blocks conventionally implemented in silicon hardware are replaced with the flexibility of software - will be crucial to achieving this convergence at an acceptable cost point.”
Silex provides Atheros AR6002 802.11a/b/g wireless SDIO modules for low-power, ultra-compact embedded solutions
SALT LAKE CITY, USA: Silex Technology America Inc., a global leader in product networking solutions, today announced two products that support 802.11a/b/g wireless technology. The products are the SX-SDPAG, a surface mount module, and the SX-SDCAG, a SDIO card module.
These products are among the first Atheros AR6002-based wireless-SDIO solutions to be delivered to the market. They are designed for OEMs who need a highly compact wireless radio/baseband solution with low power consumption.
As an Atheros Authorized Design Center (AADC), Silex can provide turnkey integration services for these products, ranging from hardware design and manufacturing to driver and supplicant development support.
The core wireless solutions are based on an Atheros AR6002 single-chip design. Silex solutions include all major components necessary to implement 802.11a/b/g wireless connectivity including a radio, baseband processor, power amplifier, low pass filter, band pass filter, crystal and a built-in EEPROM. The AR6002’s power-efficient chip design draws very low standby power and has nominal impact on battery life even in active mode.
The SX-SDPAG is designed to be directly mounted to an OEM’s printed circuit board, while SX-SDCAG comes in an SD card form factor. Both solutions are desirable for adding cost-effective wireless connectivity in low power, battery operated, mobile devices such as medical devices and mobile printers.
According to a recent report by ABI Research, the global market for Wi-Fi-enabled healthcare products will grow by 70 percent over the next five years, to an estimated $4.9 billion in 2014. The ongoing initiative for healthcare reform from the U.S. government is expected to further accelerate adoption of wireless technologies in various healthcare mobile applications.
"These two new products further enhance our ability to support the growing demand for wireless and mobile devices in various arenas including the medical industry,” said David Smith, president of Silex Technology America.
"Our customers are typically OEMs who service markets that leverage the wireless technology found in PCs, PDAs and mobile phones with much lower annual volumes. Our role is to ensure that such niche segments are adequately offered the latest Atheros technology together with our unique software options."
Eric Cheong, senior director of sales for Atheros, said, "Over the past five years, Silex has demonstrated valuable wireless software know-how by delivering a number of breakthrough solutions using Atheros products. Silex’s unique offering combined with flexible hardware supply capabilities will help us further expand our global customer base."
SX-SDPAG and SX-SDCAG are expected to be available for shipping in late December 2009.
These products are among the first Atheros AR6002-based wireless-SDIO solutions to be delivered to the market. They are designed for OEMs who need a highly compact wireless radio/baseband solution with low power consumption.
As an Atheros Authorized Design Center (AADC), Silex can provide turnkey integration services for these products, ranging from hardware design and manufacturing to driver and supplicant development support.
The core wireless solutions are based on an Atheros AR6002 single-chip design. Silex solutions include all major components necessary to implement 802.11a/b/g wireless connectivity including a radio, baseband processor, power amplifier, low pass filter, band pass filter, crystal and a built-in EEPROM. The AR6002’s power-efficient chip design draws very low standby power and has nominal impact on battery life even in active mode.
The SX-SDPAG is designed to be directly mounted to an OEM’s printed circuit board, while SX-SDCAG comes in an SD card form factor. Both solutions are desirable for adding cost-effective wireless connectivity in low power, battery operated, mobile devices such as medical devices and mobile printers.
According to a recent report by ABI Research, the global market for Wi-Fi-enabled healthcare products will grow by 70 percent over the next five years, to an estimated $4.9 billion in 2014. The ongoing initiative for healthcare reform from the U.S. government is expected to further accelerate adoption of wireless technologies in various healthcare mobile applications.
"These two new products further enhance our ability to support the growing demand for wireless and mobile devices in various arenas including the medical industry,” said David Smith, president of Silex Technology America.
"Our customers are typically OEMs who service markets that leverage the wireless technology found in PCs, PDAs and mobile phones with much lower annual volumes. Our role is to ensure that such niche segments are adequately offered the latest Atheros technology together with our unique software options."
Eric Cheong, senior director of sales for Atheros, said, "Over the past five years, Silex has demonstrated valuable wireless software know-how by delivering a number of breakthrough solutions using Atheros products. Silex’s unique offering combined with flexible hardware supply capabilities will help us further expand our global customer base."
SX-SDPAG and SX-SDCAG are expected to be available for shipping in late December 2009.
SEMATECH researchers to unveil next-generation device and process breakthroughs at IEDM
AUSTIN & ALBANY, USA: Engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs at the 55th annual IEEE International Electron Devices Meeting (IEDM) from December 7-9, 2009, at the Hilton in Baltimore, MD.
SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage—a significant process technology advancement for next-generation logic and memory technologies.
“SEMATECH continues to make critical contributions to materials and process technology advancements for next-generation logic and memory devices. The industry is always looking for cost-effective technical solutions that are practical for manufacturing and SEMATECH’s front-end engineers are working to find new ways to extend CMOS in existing markets and to create opportunities for new emerging applications,” said Raj Jammy, SEMATECH’s vice president of materials and emerging technologies.
“We are excited to share our research results with the technical community at the IEDM, which has always been a premier forum for sharing breakthrough developments in materials and process technologies for transistor and memory scaling.”
Additionally, SEMATECH will host an invitational pre-conference workshop entitled “Emerging Technologies in Solid State Devices” from December 5-6.
The two-day workshop will focus on technical and manufacturing challenges affecting emerging memory technologies, energy-efficient devices, and III-V channel materials in CMOS devices. Co-sponsored by Tokyo Electron Ltd and Aixtron AG, the workshop will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.
SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage—a significant process technology advancement for next-generation logic and memory technologies.
“SEMATECH continues to make critical contributions to materials and process technology advancements for next-generation logic and memory devices. The industry is always looking for cost-effective technical solutions that are practical for manufacturing and SEMATECH’s front-end engineers are working to find new ways to extend CMOS in existing markets and to create opportunities for new emerging applications,” said Raj Jammy, SEMATECH’s vice president of materials and emerging technologies.
“We are excited to share our research results with the technical community at the IEDM, which has always been a premier forum for sharing breakthrough developments in materials and process technologies for transistor and memory scaling.”
Additionally, SEMATECH will host an invitational pre-conference workshop entitled “Emerging Technologies in Solid State Devices” from December 5-6.
The two-day workshop will focus on technical and manufacturing challenges affecting emerging memory technologies, energy-efficient devices, and III-V channel materials in CMOS devices. Co-sponsored by Tokyo Electron Ltd and Aixtron AG, the workshop will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.
Wintegra announces sampling of WinPath3 processor family
AUSTIN, USA: Strengthening their processor offering, Wintegra announced today that their third generation processor family, the WinPath3, is now sampling to selected customers around the world. This new processor significantly extends Wintegra’s reach in the access infrastructure.
It offers performance 5 times that of the previous generation of Wintegra processors and provides the foundation for market leading products in Wireless Base Stations, Mobile Backhaul including IP and microwave, and broadband access.
Wintegra also has the broadest set of production quality software and extensive collateral and design assistance enabling rapid time to market for WinPath based infrastructure solutions.
“Wintegra, a perennial leader in the access processor market, has significantly broadened its product offering with the WinPath3 family,” said Bob Wheeler, Senior Analyst at The Linley Group. “With its strong software offering, and now with a 5 times increase in performance over its previous generation devices, Wintegra has compelling and scalable solutions for Mobile Backhaul, LTE Base Stations, and Carrier Ethernet.”
“The availability of WinPath3 is a significant milestone for Wintegra," said Kobi Ben-Zvi, Founder and Wintegra CEO. “Our vision to become the market leader in access infrastructure processing plus our continuous investment in protocol processing software and high performance, low power family of processors has resulted in a wide range of system solutions unmatched in our marketplace.”
WinPath3 devices are sampling now to major Tier 1 customers, with production qualified devices to be available in 2Q 2010. WinPath3 based Development Systems are available as well.
It offers performance 5 times that of the previous generation of Wintegra processors and provides the foundation for market leading products in Wireless Base Stations, Mobile Backhaul including IP and microwave, and broadband access.
Wintegra also has the broadest set of production quality software and extensive collateral and design assistance enabling rapid time to market for WinPath based infrastructure solutions.
“Wintegra, a perennial leader in the access processor market, has significantly broadened its product offering with the WinPath3 family,” said Bob Wheeler, Senior Analyst at The Linley Group. “With its strong software offering, and now with a 5 times increase in performance over its previous generation devices, Wintegra has compelling and scalable solutions for Mobile Backhaul, LTE Base Stations, and Carrier Ethernet.”
“The availability of WinPath3 is a significant milestone for Wintegra," said Kobi Ben-Zvi, Founder and Wintegra CEO. “Our vision to become the market leader in access infrastructure processing plus our continuous investment in protocol processing software and high performance, low power family of processors has resulted in a wide range of system solutions unmatched in our marketplace.”
WinPath3 devices are sampling now to major Tier 1 customers, with production qualified devices to be available in 2Q 2010. WinPath3 based Development Systems are available as well.
Oct. chip sales up 5.1 percent from September: SIA
SAN JOSE, USA: Worldwide sales of semiconductors rose to $21.7 billion in October, a 5.1 percent increase from September when sales were $20.6 billion, the Semiconductor Industry Association (SIA) reported today.
Sales are 3.5 percent below October 2008 when sales were $22.5 billion. Sales for the first 10 months of 2009 were $180.0 billion, a decline of 16.6 percent from the like period of 2008 when sales were $215.8 billion. All monthly sales numbers represent a three-month moving average of global semiconductor sales.
“October is historically a strong month for the semiconductor industry as electronic equipment manufacturers ramp production for the holiday season. Inventory management throughout the supply chain has been very tight, and this may extend the fourth-quarter build season by a few weeks,” Scalise continued.
“As semiconductor sales are increasingly driven by the performance of the overall global economy our sales are reflecting the improved economic conditions in our world markets. Sales increased sequentially in all geographic regions,” Scalise concluded.
Source: SIA, USA
Sales are 3.5 percent below October 2008 when sales were $22.5 billion. Sales for the first 10 months of 2009 were $180.0 billion, a decline of 16.6 percent from the like period of 2008 when sales were $215.8 billion. All monthly sales numbers represent a three-month moving average of global semiconductor sales.
“October is historically a strong month for the semiconductor industry as electronic equipment manufacturers ramp production for the holiday season. Inventory management throughout the supply chain has been very tight, and this may extend the fourth-quarter build season by a few weeks,” Scalise continued.
“As semiconductor sales are increasingly driven by the performance of the overall global economy our sales are reflecting the improved economic conditions in our world markets. Sales increased sequentially in all geographic regions,” Scalise concluded.
Source: SIA, USA
SiliconBlue Technologies first new FPGA company to ship in production volume in 20 Years
SANTA CLARA, USA: SiliconBlue Technologies, a leader in ultra-low power, single-chip, SRAM FPGAs, today announced that it has shipped production-volume quantities of its iCE65 mobileFPGA devices to more than 10 customers.
This makes SiliconBlue Technologies the first new programmable logic solutions company in over 20 years to achieve this milestone. The achievement comes as the market for highly-integrated, extremely-low power mobile applications such as feature phones, eBook readers, MIDs (mobile internet devices), and DSCs (digital still cameras) has begun explosive growth.
“As we move through the design-in process with customers, it’s apparent that our mobileFPGA devices are providing the right solution at the right time,” said Kapil Shankar, CEO of SiliconBlue. “Much as the growth of traditional FPGAs was driven by the telecom boom of the 1990’s, the growth of mobileFPGA devices is being driven by the rate of innovation in today’s exploding mobile consumer market.”
The rapid adoption of SiliconBlue’s mobileFPGA family is based on its unmatched ability to meet consumers demand for converging functions on portable battery-operated devices.
It is often difficult for hardware designers of products like feature phones and eBooks to meet this demand because of the constrained space, power and cost requirements they face. In addition, the various semiconductor products that they use are not necessarily designed to work together.
By offering high capacity, low power, small packages, and ASIC-like prices, the iCE65 mobileFPGA family delivers the time-to-market benefit of programmable logic solutions to a new and emerging market. They are enabling the creation of seamless new solutions.
Built on TSMC’s standard 65nm low-power CMOS process, SiliconBlue’s iCE65 devices are single-chip, reconfigurable, SRAM-based devices that incorporate the company’s proprietary NVCM (Non-Volatile Configuration Memory) technology. NVCM eliminates the need for an external flash PROM, making them a true ASIC alternative.
Devices are available in the most advanced small-form-factor packaging, including the industry’s first and only Wafer Level Chip Scale Package (WLCSP). SiliconBlue’s complete design environment includes the iCEcube VHDL and Verilog-based development software, and the iCEman evaluation kit.
In addition, the company works closely with its supply partners to meet the highest levels of product quality and production readiness.
This makes SiliconBlue Technologies the first new programmable logic solutions company in over 20 years to achieve this milestone. The achievement comes as the market for highly-integrated, extremely-low power mobile applications such as feature phones, eBook readers, MIDs (mobile internet devices), and DSCs (digital still cameras) has begun explosive growth.
“As we move through the design-in process with customers, it’s apparent that our mobileFPGA devices are providing the right solution at the right time,” said Kapil Shankar, CEO of SiliconBlue. “Much as the growth of traditional FPGAs was driven by the telecom boom of the 1990’s, the growth of mobileFPGA devices is being driven by the rate of innovation in today’s exploding mobile consumer market.”
The rapid adoption of SiliconBlue’s mobileFPGA family is based on its unmatched ability to meet consumers demand for converging functions on portable battery-operated devices.
It is often difficult for hardware designers of products like feature phones and eBooks to meet this demand because of the constrained space, power and cost requirements they face. In addition, the various semiconductor products that they use are not necessarily designed to work together.
By offering high capacity, low power, small packages, and ASIC-like prices, the iCE65 mobileFPGA family delivers the time-to-market benefit of programmable logic solutions to a new and emerging market. They are enabling the creation of seamless new solutions.
Built on TSMC’s standard 65nm low-power CMOS process, SiliconBlue’s iCE65 devices are single-chip, reconfigurable, SRAM-based devices that incorporate the company’s proprietary NVCM (Non-Volatile Configuration Memory) technology. NVCM eliminates the need for an external flash PROM, making them a true ASIC alternative.
Devices are available in the most advanced small-form-factor packaging, including the industry’s first and only Wafer Level Chip Scale Package (WLCSP). SiliconBlue’s complete design environment includes the iCEcube VHDL and Verilog-based development software, and the iCEman evaluation kit.
In addition, the company works closely with its supply partners to meet the highest levels of product quality and production readiness.
AMCC becomes AppliedMicro
SUNNYVALE, USA: Applied Micro Circuits Corp., a global leader in energy conscious computing and communications solutions, today announced its new name as AppliedMicro to reflect the company’s drive for breakthrough energy efficiency and cost optimized semiconductor devices that will propel the company into new growth markets.
In keeping with the 30-year AMCC heritage as an innovator in high-speed connectivity and high performance embedded processing, AppliedMicro will remain dedicated to its customers in the telco, datacenter and enterprise markets, while increasing market share by striving to reduce the power consumption of its products by as much as 50 percent.
“While higher performance continues to be an industry driver, energy efficiency will play a more prominent role in the design considerations and purchasing decisions for our customers in the data center and telecommunications industries,” said Dr. Paramesh Gopi, President and Chief Executive Officer of AppliedMicro.
“We are driving fundamental technology innovation that will radically lower the energy consumption of enterprise, datacenter and small business systems while simultaneously providing significant cost savings. Our computing and communications silicon solutions will have pioneering performance and the lowest power footprint in their class.”
Under the new name, AppliedMicro will leverage its substantial intellectual property, patent portfolio and engineering resources to pursue aggressive migration to advanced manufacturing processes and design techniques for its semiconductor devices that lead the market in optical transport, network switches and, routers, data center and enterprise systems.
A migration to open foundry manufacturing for AppliedMicro’s Power Architecture microprocessor line is also one example of the company’s drive toward low-power devices that will enable the company to achieve lower costs for its products and open up design opportunities for consumer and small-to-medium business systems.
In addition, new design centers in India and Vietnam will assist the company in bringing advanced hardware and software solutions to market as most of the company’s engineering resources remain at its Sunnyvale headquarters.
“Growth in both the embedded systems and communications infrastructure markets are predicted at fairly robust growth rates over the next five years according to IDC research,” said Shane Rau, industry analyst for IDC. “Integrated circuits for systems in this market that feature low heat dissipation levels are drawing higher interest because a major industry goal is to reduce data center operating costs by using less air conditioning.”
“Our plan to rapidly migrate our IC designs to 40-nanometer and 28-nanometer manufacturing processes is a key part of our strategy to introduce the most advanced, power efficient devices on the market,” Gopi said.
“We are breaking new ground by applying mobile and handheld design techniques to telecommunications and infrastructure silicon solutions, producing unprecedented energy efficiencies without compromising performance. Applied Micro will set new standards for low-power ultra-high performance processors, framers, mappers, physical layer and optical datacenter devices that will drive a new era of energy efficient infrastructure.”
The shift to the AppliedMicro name began when Gopi assumed the executive leadership of the company in January after serving for one year as the chief operating officer.
The company sold its 3ware storage system division so that it could concentrate on its fabless semiconductor business model. New executive leadership was also brought in to help the company focus on advances in microprocessor and transport development. The company’s legal name remains Applied Micro Circuits Corporation and its ticker symbol on the NASDAQ exchanges remains AMCC.
In keeping with the 30-year AMCC heritage as an innovator in high-speed connectivity and high performance embedded processing, AppliedMicro will remain dedicated to its customers in the telco, datacenter and enterprise markets, while increasing market share by striving to reduce the power consumption of its products by as much as 50 percent.
“While higher performance continues to be an industry driver, energy efficiency will play a more prominent role in the design considerations and purchasing decisions for our customers in the data center and telecommunications industries,” said Dr. Paramesh Gopi, President and Chief Executive Officer of AppliedMicro.
“We are driving fundamental technology innovation that will radically lower the energy consumption of enterprise, datacenter and small business systems while simultaneously providing significant cost savings. Our computing and communications silicon solutions will have pioneering performance and the lowest power footprint in their class.”
Under the new name, AppliedMicro will leverage its substantial intellectual property, patent portfolio and engineering resources to pursue aggressive migration to advanced manufacturing processes and design techniques for its semiconductor devices that lead the market in optical transport, network switches and, routers, data center and enterprise systems.
A migration to open foundry manufacturing for AppliedMicro’s Power Architecture microprocessor line is also one example of the company’s drive toward low-power devices that will enable the company to achieve lower costs for its products and open up design opportunities for consumer and small-to-medium business systems.
In addition, new design centers in India and Vietnam will assist the company in bringing advanced hardware and software solutions to market as most of the company’s engineering resources remain at its Sunnyvale headquarters.
“Growth in both the embedded systems and communications infrastructure markets are predicted at fairly robust growth rates over the next five years according to IDC research,” said Shane Rau, industry analyst for IDC. “Integrated circuits for systems in this market that feature low heat dissipation levels are drawing higher interest because a major industry goal is to reduce data center operating costs by using less air conditioning.”
“Our plan to rapidly migrate our IC designs to 40-nanometer and 28-nanometer manufacturing processes is a key part of our strategy to introduce the most advanced, power efficient devices on the market,” Gopi said.
“We are breaking new ground by applying mobile and handheld design techniques to telecommunications and infrastructure silicon solutions, producing unprecedented energy efficiencies without compromising performance. Applied Micro will set new standards for low-power ultra-high performance processors, framers, mappers, physical layer and optical datacenter devices that will drive a new era of energy efficient infrastructure.”
The shift to the AppliedMicro name began when Gopi assumed the executive leadership of the company in January after serving for one year as the chief operating officer.
The company sold its 3ware storage system division so that it could concentrate on its fabless semiconductor business model. New executive leadership was also brought in to help the company focus on advances in microprocessor and transport development. The company’s legal name remains Applied Micro Circuits Corporation and its ticker symbol on the NASDAQ exchanges remains AMCC.
MoSys' silicon proven 40nm DDR3 and DDR3/2 combo PHYs with support for datarates up to 2133 Mbps
SUNNYVALE, USA: MoSys Inc., a leading supplier of high-density embedded memory and high-datarate parallel and serial interface IP, today announced the availability of its silicon-proven DDR3 and DDR3/2 combo PHYs.
MoSys’ fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3/2 DRAM devices. The DDR3/2 PHYs can achieve datarates up to 1600Mbps in a wirebond package and 2133Mbps in flip chip packaging, making them well-suited for both high -performance and cost-sensitive designs.
“Our high-performance memory controllers and predictable protocol verification portfolio are the industry’s most widely used, silicon-proven solutions,” said David Lin, Vice President of Marketing at Denali Software Inc. “MoSys' DDR3/2 Combo PHY extends our ability to provide best-in-class, end-to-end memory interconnect solutions to our mutual customers.”
“DDR3 is rapidly gaining adoption as the next generation of the DDR memory interface,” said David DeMaria, Vice President of Business Operations at MoSys. "The availability of our DDR3/2 Combo PHY and its seamless interoperability with Denali’s Memory Controller ensures speedy time-to-market for our customers’ chip designs."
"The high speed interface requirements for our ASICs are demanding," said Anil Mankar, Senior Vice President of VLSI Engineering for Mindspeed Technologies. “We selected the DDR3 solution from MoSys because it precisely met our requirements."
MoSys’ DFI 2.1 compliant DDR 3/2 PHY product is available to chip designers using 40nm and 65nm processes. MoSys’s DDR 3/2 Combo PHY solution is available in both wirebond and flipchip configurations. Offering a choice of 1.8V or 2.5V IO FETs, the DDR PHYs support datarates up to 2133Mbps.
MoSys’ fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3/2 DRAM devices. The DDR3/2 PHYs can achieve datarates up to 1600Mbps in a wirebond package and 2133Mbps in flip chip packaging, making them well-suited for both high -performance and cost-sensitive designs.
“Our high-performance memory controllers and predictable protocol verification portfolio are the industry’s most widely used, silicon-proven solutions,” said David Lin, Vice President of Marketing at Denali Software Inc. “MoSys' DDR3/2 Combo PHY extends our ability to provide best-in-class, end-to-end memory interconnect solutions to our mutual customers.”
“DDR3 is rapidly gaining adoption as the next generation of the DDR memory interface,” said David DeMaria, Vice President of Business Operations at MoSys. "The availability of our DDR3/2 Combo PHY and its seamless interoperability with Denali’s Memory Controller ensures speedy time-to-market for our customers’ chip designs."
"The high speed interface requirements for our ASICs are demanding," said Anil Mankar, Senior Vice President of VLSI Engineering for Mindspeed Technologies. “We selected the DDR3 solution from MoSys because it precisely met our requirements."
MoSys’ DFI 2.1 compliant DDR 3/2 PHY product is available to chip designers using 40nm and 65nm processes. MoSys’s DDR 3/2 Combo PHY solution is available in both wirebond and flipchip configurations. Offering a choice of 1.8V or 2.5V IO FETs, the DDR PHYs support datarates up to 2133Mbps.
Kilopass appoints Juan Chapa as VP of Worldwide Sales
SANTA CLARA, USA: Kilopass Technology, a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), today announced the appointment of Juan Chapa as Vice President of Worldwide Sales, effective immediately.
“I am thrilled to welcome Juan to our executive team,” said Charlie Cheng, CEO of Kilopass Technology. “2009 was a tough year for Kilopass, but with a tremendous team effort in the second half of the year, we were able to double our business compared to 2008. Juan’s leadership will ensure that we capitalize on the business momentum and continue to grow. He brings with him extensive semiconductor IP business experience and a strong network of relationships to expand Kilopass’ footprint.”
Juan Chapa has over 15 years of experience in semiconductor OEM and Distribution sales, including seven years in the semiconductor IP space. He was Senior Director of North America sales at Artisan/ARM, and most recently, Juan was North America VP of Sales at Tensilica where his team drove 55 percent of the Tensilica’s total revenue.
He has also held various management positions at Mosel/Vitelic Semi, Cypress Semi, Wyle Labs, and Xeorx Corp.
“I’m excited to join the Kilopass team,” said the new VP of Worldwide sales, Juan Chapa. “Kilopass has a loyal customer base, proven product, and an exciting roadmap. I'm confident that together with the management team we can exceed our sales plan for 2010.”
“I am thrilled to welcome Juan to our executive team,” said Charlie Cheng, CEO of Kilopass Technology. “2009 was a tough year for Kilopass, but with a tremendous team effort in the second half of the year, we were able to double our business compared to 2008. Juan’s leadership will ensure that we capitalize on the business momentum and continue to grow. He brings with him extensive semiconductor IP business experience and a strong network of relationships to expand Kilopass’ footprint.”
Juan Chapa has over 15 years of experience in semiconductor OEM and Distribution sales, including seven years in the semiconductor IP space. He was Senior Director of North America sales at Artisan/ARM, and most recently, Juan was North America VP of Sales at Tensilica where his team drove 55 percent of the Tensilica’s total revenue.
He has also held various management positions at Mosel/Vitelic Semi, Cypress Semi, Wyle Labs, and Xeorx Corp.
“I’m excited to join the Kilopass team,” said the new VP of Worldwide sales, Juan Chapa. “Kilopass has a loyal customer base, proven product, and an exciting roadmap. I'm confident that together with the management team we can exceed our sales plan for 2010.”
Virtutech expands international growth by opening China subsidiary
SAN JOSE, USA: Virtutech Inc., the leader in virtualized systems development (VSD), today announced that it has established a subsidiary in China to support its expanding customers and partners.
Based in Shanghai, Virtutech Ltd. will provide a direct channel to regional businesses and enhance support for existing Simics customers in the Asia Pacific market. Virtutech Ltd. is part of the company’s continuing global expansion strategy, and reflects its commitment to deliver the most advanced virtual platform and simulation-based solution to OEM and semiconductor companies who recognize that virtualization of development is the necessary breakthrough to overcome technical and business challenges.
“Virtutech Ltd. extends our commitment to supporting Simics users and partners throughout China,” said Greg Lund, vice president, Asia Pacific Region, Virtutech, Inc. “Our comprehensive approach to electronics systems design, and to driving the adoption of VSD will lower project risk and improve the quality of software products in the thriving Chinese market.”
Virtutech has been growing its business in China since 2007, when it partnered with several Chinese and American based companies and organizations, including, Freescale, Huawei, Power.org, RMI, Tensilica, Vision Microsystems and Wind River.
Demand for Simics has been especially strong in China, where the rapid growth of the embedded software industry has created the need for a solution that fully leverages multi-core architectures, and runs complex simulations of semiconductor and OEM environments.
Based in Shanghai, Virtutech Ltd. will provide a direct channel to regional businesses and enhance support for existing Simics customers in the Asia Pacific market. Virtutech Ltd. is part of the company’s continuing global expansion strategy, and reflects its commitment to deliver the most advanced virtual platform and simulation-based solution to OEM and semiconductor companies who recognize that virtualization of development is the necessary breakthrough to overcome technical and business challenges.
“Virtutech Ltd. extends our commitment to supporting Simics users and partners throughout China,” said Greg Lund, vice president, Asia Pacific Region, Virtutech, Inc. “Our comprehensive approach to electronics systems design, and to driving the adoption of VSD will lower project risk and improve the quality of software products in the thriving Chinese market.”
Virtutech has been growing its business in China since 2007, when it partnered with several Chinese and American based companies and organizations, including, Freescale, Huawei, Power.org, RMI, Tensilica, Vision Microsystems and Wind River.
Demand for Simics has been especially strong in China, where the rapid growth of the embedded software industry has created the need for a solution that fully leverages multi-core architectures, and runs complex simulations of semiconductor and OEM environments.
Diamond Microwave Devices closes GBP1.3m commercialisation round
LEEDS, ENGLAND: Diamond Microwave Devices (DMD), a spin out from the diamond electronics team in Element Six Technologies (E6), has closed a GBP1.3m equity investment from a consortium consisting of Oxford Technology Management, YFM via the Partnership Investment Fund, The ERA Foundation and two private investors.
During the course of 2009, DMD has made various performance breakthroughs in its diamond-based transistor technology and this investment round will be used to develop and build power amplifier modules for customer trialling during 2010. The DMD diamond transistor technology will enable the move to low cost, lightweight solid-state amplifiers in high power, high frequency applications such as radar, communications, SATCOMS, and electronic warfare.
"This new investment signals the next step for DMD. It will allow the company to progress with its plans to commercialise its ground-breaking technology, says Brendon Grunewald, head of E6 Ventures.
"DMD has gathered an experienced and fast-moving team both inside the company and outside with its choice of partners, to develop the product in close concert with its first customer. DMD's customers will get a step change in performance per kg & per dollar - both important to deliver a clear capability advantage. It has all the right ingredients of a high potential venture," notes David Denny, partner at lead investor Oxford Technology ECF.
Element Six is the world's leading supplier of industrial Diamond supermaterials. It is an international company with its head office registered in Luxembourg and processing and manufacturing facilities in Germany, Ireland, UK, Netherlands, Sweden, South Africa and China. Its business encompasses four divisions: Oil & Gas, Advanced Materials, Hard Materials and Technologies and the company manufactures Diamond using high pressure high temperature (HPHT) synthesis and chemical vapour deposition (CVD).
During the course of 2009, DMD has made various performance breakthroughs in its diamond-based transistor technology and this investment round will be used to develop and build power amplifier modules for customer trialling during 2010. The DMD diamond transistor technology will enable the move to low cost, lightweight solid-state amplifiers in high power, high frequency applications such as radar, communications, SATCOMS, and electronic warfare.
"This new investment signals the next step for DMD. It will allow the company to progress with its plans to commercialise its ground-breaking technology, says Brendon Grunewald, head of E6 Ventures.
"DMD has gathered an experienced and fast-moving team both inside the company and outside with its choice of partners, to develop the product in close concert with its first customer. DMD's customers will get a step change in performance per kg & per dollar - both important to deliver a clear capability advantage. It has all the right ingredients of a high potential venture," notes David Denny, partner at lead investor Oxford Technology ECF.
Element Six is the world's leading supplier of industrial Diamond supermaterials. It is an international company with its head office registered in Luxembourg and processing and manufacturing facilities in Germany, Ireland, UK, Netherlands, Sweden, South Africa and China. Its business encompasses four divisions: Oil & Gas, Advanced Materials, Hard Materials and Technologies and the company manufactures Diamond using high pressure high temperature (HPHT) synthesis and chemical vapour deposition (CVD).
Renesas sampling SH-Mobile application engine 4
SAN JOSE, USA: Renesas Technology America Inc. today announced that it is sampling the SH-Mobile Application Engine 4 (SH73720), an ARM Cortex A8*1 based application engine running at maximum 1GHz, targeted for next generation mobile phone and mobile device implementations.
With the integration of various dedicated processing engines, the device features ultimate multimedia capabilities such as full HD 1080p video recording, playback at 30fps, and high-speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience.
Leveraging on Renesas’ market proven Image Signal Processor (ISP) technology, the SH-Mobile Application Engine 4 provides a state-of-the art 16Mpixel ISP for best visual quality while supporting full HD 1080p movie processing. Fabricated in Renesas’ optimized 45nm low power process and integrating a wealth of new and innovative power saving schemes, it exceeds the stringent power budget requirements of mobile phones.
“With broadband wireless access like UMTS/HSPA or LTE, customers can have the Internet at their fingertips wherever and whenever. Access to music, videos and games with mobile phones becomes as simple as it became on the PC a few years ago,” says Shinichi Yoshioka, General Manager of System Solution Business Unit2, System Solution Business Group, Renesas Technology Corp.
“Renesas has developed the SH-Mobile Application Engine 4, as the first device of the SH-Mobile Application Engine Series, in a new class of application processors to offer an entirely new user experience on mobile computers and to solve the conflicts around creating an exciting multimedia experience within the low power budget of mobile devices.”
The SH-Mobile Application Engine 4 is based on an ARM Cortex-A8 core operating at maximum 1GHz. Leveraging Renesas’ vast experience of highly integrated SoC systems, a competitive SoC process and an innovative design architecture, this device aims for one of the industry’s most efficient ARM Cortex-A8 implementations providing ample processing performance for next generation applications, while pursuing the ultimate low power consumption that enables an entirely new user experience on mobile devices.
For the ultimate multimedia experience, the SH-Mobile Application Engine 4 incorporates a variety of dedicated processing engines. An integrated ISP supports 16M pixel still images and full HD 1080p movie images.
A dedicated high-performance multi-codec video processing unit for ultra-low power video processing enables the device to support full HD 1080p multi-standard video use cases such as encoding (recording) and decoding (playback) of full HD 1080p video at 30 frames per second (fps).
Combined with various multi-phased visual engines, such as IP for edge enhancement or median filtering, the realization of high quality HD images and videos reaches levels which consumers will not have experienced before on mobile devices.
To support high-speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience, the device is equipped with a powerful POWERVR SGX*2 3D graphics engine, licensed from Imagination Technologies, supporting graphic APIs such as OpenGL*3 ES1.1/2.0 and Open VG. To round off the multimedia experience, the SH-Mobile Application Engine 4 also incorporates a highly sophisticated audio subsystem enabling well over 100 hours of audio playback on a standard mobile phone battery.
For design flexibility and reduced system BOM, the SH-Mobile Application Engine 4 includes a wide variety of on-chip peripheral functions and connectivity interfaces.
This includes two USB 2.0 Host/Function modules (with high-speed data transfer mode support), three SD host controllers with support for high-speed data transfer mode and a 24-bit TFT color LCD controller supporting up to WXGA+ display sizes. Furthermore, a PAL/NTSC encoder and an HDMI transmitter are integrated together with a complete HDMI v1.3a & CVBS TV-Out interface.
The SH-Mobile Application Engine 4 is packaged in a 0.4mm pitch, 12mm x 12mm BGA package that allows package-on-package vertical stacking of low power, multiple chip package (MCP) memory such as LP DDR2, greatly reducing the overall footprint of the memory and processor combination.
With the integration of various dedicated processing engines, the device features ultimate multimedia capabilities such as full HD 1080p video recording, playback at 30fps, and high-speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience.
Leveraging on Renesas’ market proven Image Signal Processor (ISP) technology, the SH-Mobile Application Engine 4 provides a state-of-the art 16Mpixel ISP for best visual quality while supporting full HD 1080p movie processing. Fabricated in Renesas’ optimized 45nm low power process and integrating a wealth of new and innovative power saving schemes, it exceeds the stringent power budget requirements of mobile phones.
“With broadband wireless access like UMTS/HSPA or LTE, customers can have the Internet at their fingertips wherever and whenever. Access to music, videos and games with mobile phones becomes as simple as it became on the PC a few years ago,” says Shinichi Yoshioka, General Manager of System Solution Business Unit2, System Solution Business Group, Renesas Technology Corp.
“Renesas has developed the SH-Mobile Application Engine 4, as the first device of the SH-Mobile Application Engine Series, in a new class of application processors to offer an entirely new user experience on mobile computers and to solve the conflicts around creating an exciting multimedia experience within the low power budget of mobile devices.”
The SH-Mobile Application Engine 4 is based on an ARM Cortex-A8 core operating at maximum 1GHz. Leveraging Renesas’ vast experience of highly integrated SoC systems, a competitive SoC process and an innovative design architecture, this device aims for one of the industry’s most efficient ARM Cortex-A8 implementations providing ample processing performance for next generation applications, while pursuing the ultimate low power consumption that enables an entirely new user experience on mobile devices.
For the ultimate multimedia experience, the SH-Mobile Application Engine 4 incorporates a variety of dedicated processing engines. An integrated ISP supports 16M pixel still images and full HD 1080p movie images.
A dedicated high-performance multi-codec video processing unit for ultra-low power video processing enables the device to support full HD 1080p multi-standard video use cases such as encoding (recording) and decoding (playback) of full HD 1080p video at 30 frames per second (fps).
Combined with various multi-phased visual engines, such as IP for edge enhancement or median filtering, the realization of high quality HD images and videos reaches levels which consumers will not have experienced before on mobile devices.
To support high-speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience, the device is equipped with a powerful POWERVR SGX*2 3D graphics engine, licensed from Imagination Technologies, supporting graphic APIs such as OpenGL*3 ES1.1/2.0 and Open VG. To round off the multimedia experience, the SH-Mobile Application Engine 4 also incorporates a highly sophisticated audio subsystem enabling well over 100 hours of audio playback on a standard mobile phone battery.
For design flexibility and reduced system BOM, the SH-Mobile Application Engine 4 includes a wide variety of on-chip peripheral functions and connectivity interfaces.
This includes two USB 2.0 Host/Function modules (with high-speed data transfer mode support), three SD host controllers with support for high-speed data transfer mode and a 24-bit TFT color LCD controller supporting up to WXGA+ display sizes. Furthermore, a PAL/NTSC encoder and an HDMI transmitter are integrated together with a complete HDMI v1.3a & CVBS TV-Out interface.
The SH-Mobile Application Engine 4 is packaged in a 0.4mm pitch, 12mm x 12mm BGA package that allows package-on-package vertical stacking of low power, multiple chip package (MCP) memory such as LP DDR2, greatly reducing the overall footprint of the memory and processor combination.
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